ATTINY84-15MZ Atmel, ATTINY84-15MZ Datasheet - Page 112

MCU AVR 8K FLASH 15MHZ 20-QFN

ATTINY84-15MZ

Manufacturer Part Number
ATTINY84-15MZ
Description
MCU AVR 8K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets

Specifications of ATTINY84-15MZ

Package / Case
20-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
512 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
512 x 8
Program Memory Size
8KB (8K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY84-15MZ
Manufacturer:
ATMEL
Quantity:
480
Part Number:
ATTINY84-15MZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
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14.11 Register Description
14.11.1
112
Atmel ATtiny24/44/84 [Preliminary]
TCCR1A – Timer/Counter1 Control Register A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the output compare pins' (OC1A and OC1B, respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to logical one, the OC1A
output overrides the normal port functionality of the I/O pin it is connected to. If one or both of
the COM1B1:0 bit are written to logical one, the OC1B output overrides the normal port func-
tionality of the I/O pin it is connected to. However, note that the data direction register (DDR)
bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver.
When OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent
on the WGM13:0 bit settings.
when the WGM13:0 bits are set to a normal or CTC mode (non-PWM).
Table 14-1.
Table 14-2 on page 112
to the fast PWM mode.
Table 14-2.
Note:
Bit
0x2F (0x4F)
Read/Write
Initial Value
COM1A1/COM1B1
COM1A1/COM1B1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
0
0
1
1
0
0
1
1
this case the compare match is ignored, but the set or clear is done at BOTTOM. See
PWM Mode” on page 103
COM1A1
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
R/W
7
0
COM1A0
COM1A0/COM1B0
COM1A0/COM1B0
shows the COM1x1:0 bit functionality when the WGM13:0 bits are set
R/W
6
0
Table 14-1 on page 112
0
1
0
1
0
1
0
1
COM1B1
R/W
for more details.
5
0
COM1B0
R/W
4
0
Description
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to
low level).
Set OC1A/OC1B on Compare Match (Set output to
high level).
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13=0: Normal port operation, OC1A/OC1B
disconnected.
WGM13=1: Toggle OC1A on Compare Match, OC1B
reserved.
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at BOTTOM (non-inverting mode)
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at BOTTOM (inverting mode)
(1)
R
3
0
shows the COM1x1:0 bit functionality
R
2
0
WGM11
R/W
1
0
WGM10
R/W
7701D–AVR–09/10
0
0
TCCR1A
“Fast

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