ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 86

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.9.2
Figure 4-23. Timing of Pin Change Interrupts
4.9.3
4.9.3.1
86
Atmel ATA6616/ATA6617
Pin Change Interrupt Timing
PCINT[i]
External Interrupts Register Description
pin
External Interrupt Control Register A – EICRA
clk
pcint_set/flag
PCINT[i] pin
pcint_in[i]
pcint_syn
pin_sync
pin_lat
D
LE
PCIF
Q
clk
n
pin_lat
An example of timing of a pin change interrupt is shown in
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 7..4 – Res: Reserved Bits
These bits are unused bits in the Atmel
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Initial Value
Read/Write
D
Bit
Q
pin_sync
(of PCMSK
R
7
–
0
PCINT[i] bit
n
Table
)
R
6
–
0
pcint_in[i]
4-21. The value on the INT1 pin is sampled before detecting
R
5
–
0
0
7
®
ATtiny87/167, and will always read as zero.
clk
R
4
–
0
D
ISC11
Q
R/W
pcint_sync
3
0
D
Figure
ISC10
R/W
Q
2
0
pcint_set/flag
4-23.
D
ISC01
R/W
1
0
Q
(interrupt flag)
PCIF
ISC00
R/W
n
0
0
9132D–AUTO–12/10
EICRA