ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 232

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.18.12.3
232
Atmel ATA6616/ATA6617
ADCL and ADCH – The ADC Data Register
Table 4-60.
ADLAR = 0
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently,
if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the
result is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
on page
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
226.
ADC Prescaler Selections
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
0
0
ADPS1
ADC6
ADC8
ADC0
0
0
1
1
0
0
1
1
14
14
R
R
R
R
–
6
0
0
6
0
0
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
ADPS0
0
1
0
1
0
1
0
1
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
ADC3
ADC5
11
11
R
R
–
3
0
0
R
R
–
3
0
0
ADC2
ADC4
10
10
R
R
–
2
0
0
R
R
–
2
0
0
Division Factor
“ADC Conversion Result”
ADC9
ADC1
ADC3
R
R
R
R
9
1
0
0
9
–
1
0
0
128
16
32
64
2
2
4
8
ADC8
ADC0
ADC2
R
R
8
0
0
0
R
R
9132D–AUTO–12/10
8
–
0
0
0
ADCH
ADCL
ADCH
ADCL