ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 178

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Atmel ATA6616/ATA6617
Figure 4-65. Two-wire Mode Operation, Simplified Diagram
Figure 4-65
Slave. It is only the physical layer that is shown since the system operation is highly depen-
dent of the communication scheme used. The main differences between the Master and Slave
operation at this level, is the serial clock generation which is always done by the Master, and
only the Slave uses the clock control unit. Clock generation must be implemented in software,
but the shift operation is done automatically by both devices. Note that only clocking on nega-
tive edge for shifting data is of practical use in this mode. The slave can insert wait states at
start or end of transfer by forcing the SCL clock low. This means that the Master must always
check if the SCL line was actually released after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that
the transfer is completed. The clock is generated by the master by toggling the USCK pin via
the PORT Register.
The data direction is not given by the physical layer. A protocol, like the one used by the
TWI-bus, must be implemented to control the data flow.
SLAVE
MASTER
shows two USI units operating in Two-wire mode, one as Master and one as
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
Control Unit
Two-wire
Clock
PORTxn
HOLD
SCL
SDA
SCL
SDA
SCL
9132D–AUTO–12/10
VCC