ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 263

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.22.8.1
9132D–AUTO–12/10
Serial Programming Algorithm
Table 4-78.
When programming the EEPROM, an auto-erase cycle is built into the self-timed program-
ming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the Atmel
SCK.
When reading data from the Atmel ATtiny87/167, data is clocked on the falling edge of SCK.
See
To program and verify the Atmel ATtiny87/167 in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte
Figure 4-104
Apply power between Vcc and GND while RESET and SCK are set to “0”. In some
systems, the programmer can not guarantee that SCK is held low during power-up. In
this case, RESET must be given a positive pulse of at least two CPU clock cycles
duration after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not,
all four bytes of the instruction must be transmitted. If the 0x53 did not echo back,
give RESET a positive pulse and issue a new Programming Enable command.
at a time by supplying the 5LSB of the address and data together with the Load Pro-
gram memory Page instruction. To ensure correct loading of the page, the data low
byte must be loaded before data high byte is applied for a given address. The Pro-
gram memory Page is stored by loading the Write Program memory Page instruction
with the 6MSB of the address. If polling (RDY/BSY) is not used, the user must wait at
least t
programming interface before the Flash write operation completes can result in incor-
rect programming.
Symbol
MOSI
MISO
SCK
WD_FLASH
Pin Mapping Serial Programming
and
before issuing the next page. (See
Figure 4-105
Pin Name
PA4
PA2
PA5
ck
ck
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
for timing details.
®
I/O Function
O
I
I
ATtiny87/167, data is clocked on the rising edge of
Serial Data In
Serial Data Out
Serial Clock
Atmel ATA6616/ATA6617
Table
4-79) Accessing the serial
Table 4-80 on page
ck
ck
>= 12MHz
>= 12MHz
265):
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