ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 144

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.13.7.1
4.13.7.2
4.13.7.3
4.13.8
144
Atmel ATA6616/ATA6617
Compare Match Output Unit
Force Output Compare
Compare Match Blocking by TCNT1 Write
Using the Output Compare Unit
In non-PWM Waveform Generation modes, the match output of the comparator can be forced
by writing a one to the Force Output Compare (FOC1A/B) bit. Forcing compare match will not
set the OCF1A/B flag or reload/clear the timer, but the OC1A/Bi pins will be updated as if a
real compare match had occurred (the COM1A/B1:0 bits settings define whether the OC1A/Bi
pins are set, cleared or toggled - if the respective OCnxi bit is set).
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next
timer clock cycle, even when the timer is stopped. This feature allows OCR1A/B to be initial-
ized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock
is enabled.
Since writing TCNT1 in any mode of operation will block all compare matches for one timer
clock cycle, there are risks involved when changing TCNT1 when using any of the Output
Compare channels, independent of whether the Timer/Counter is running or not. If the value
written to TCNT1 equals the OCR1A/B value, the compare match will be missed, resulting in
incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with
variable TOP values. The compare match for the TOP will be ignored and the counter will con-
tinue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter
is downcounting.
The setup of the OC1A/B should be performed before setting the Data Direction Register for
the port pin to output. The easiest way of setting the OC1A/B value is to use the Force Output
Compare (FOC1A/B) strobe bits in Normal mode. The OC1A/B Register keeps its value even
when changing between Waveform Generation modes.
Be aware that the COM1A/B1:0 bits are not double buffered together with the compare value.
Changing the COM1A/B1:0 bits will take effect immediately.
The Compare Output mode (COM1A/B1:0) bits have two functions. The Waveform Generator
uses the COM1A/B1:0 bits for defining the Output Compare (OC1A/B) state at the next com-
pare match. Secondly the COM1A/B1:0 and OCnxi bits control the OC1A/Bi pin output source.
Figure 4-49
bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the
parts of the general I/O port control registers (DDR and PORT) that are affected by the
COM1A/B1:0 and OCnxi bits are shown. When referring to the OC1A/B state, the reference is
for the internal OC1A/B Register, not the OC1A/Bi pin. If a system reset occur, the OC1A/B
Register is reset to “0”.
shows a simplified schematic of the logic affected by the COM1A/B1:0 and OCnxi
9132D–AUTO–12/10