ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 206

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.16.6.3
206
Atmel ATA6616/ATA6617
LIN Enable Interrupt Register - LINENIR
• Bit 3 - LERR: Error Interrupt
• Bit 2 - LIDOK: Identifier Interrupt
• Bit 1 - LTXOK: Transmit Performed Interrupt
• Bit 0 - LRXOK: Receive Performed Interrupt
• Bits 7:4 - Reserved Bits
• Bit 3 - LENERR: Enable Error Interrupt
Initial Value
Read/Write
It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective
enable bit - LENERR - is set in LINENIR.
The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also
resets all LINERR bits.
In UART mode, this bit is also cleared by reading LINDAT.
This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR.
The user clears this bit by writing 1, in order to reset this interrupt.
This bit generates an interrupt if its respective enable bit - LENTXOK - is set in LINENIR.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by writing LINDAT.
This bit generates an interrupt if its respective enable bit - LENRXOK - is set in LINENIR.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by reading LINDAT.
Bit
– 0 = No error,
– 1 = An error has occurred.
– 0 = No identifier,
– 1 = Slave task: Identifier present, master task: Tx Header complete.
– 0 = No Tx,
– 1 = Tx Response complete.
– 0 = No Rx
– 1 = Rx Response complete.
– These bits are reserved for future use. For compatibility with future devices, they
– 0 = Error interrupt masked,
– 1 = Error interrupt enabled.
must be written to zero when LINENIR is written.
R
7
0
-
R
6
0
-
R
5
0
-
R
4
0
-
LENERR
R/W
3
0
LENIDOK LENTXOK LENRXOK LINENIR
R/W
2
0
R/W
1
0
R/W
0
0
9132D–AUTO–12/10