ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 155
ATA6617-P3QW
Manufacturer Part Number
ATA6617-P3QW
Description
MCU W/LIN TX/5V REG/WTCDG 38VQFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6617-EK.pdf
(308 pages)
Specifications of ATA6617-P3QW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6617-P3QW
Manufacturer:
ATMEL
Quantity:
3 500
Part Number:
ATA6617-P3QW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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4.13.10
9132D–AUTO–12/10
Timer/Counter Timing Diagrams
In phase and frequency correct PWM mode, the compare units allow generation of PWM
waveforms on the OC1A/B pins. Setting the COM1A/B1:0 bits to two will produce a
non-inverted PWM and an inverted PWM output can be generated by setting the COM1A/B1:0
to three (See
if the data direction for the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The
PWM waveform is generated by setting (or clearing) the OC1A/B Register at the compare
match between OCR1A/B and TCNT1 when the counter increments, and clearing (or setting)
the OC1A/B Register at compare match between OCR1A/B and TCNT1 when the counter
decrements. The PWM frequency for the output when using phase and frequency correct
PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represents special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1A/B is set equal to BOT-
TOM the output will be continuously low and if set equal to TOP the output will be set to high
for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR1A/B Register is updated with the OCR1A/B buffer value
(only for modes utilizing double buffering).
of OCF1A/B.
Figure 4-54. Timer/Counter Timing Diagram, Setting of OCF1A/B, No Prescaling
f
OCnxPFCPWM
TCNTn
OCRnx
OCFnx
(clk
=
clk
clk
Table on page
I/O
I/O
Tn
--------------------------------- -
2
/1)
f
N
clk_I/O
TOP
OCRnx - 1
158). The actual OC1A/B value will only be visible on the port pin
OCRnx
Figure 4-54
OCRnx Value
Atmel ATA6616/ATA6617
shows a timing diagram for the setting
OCRnx + 1
T1
) is therefore shown as a
OCRnx + 2
155
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