ATA6617-P3QW Atmel, ATA6617-P3QW Datasheet - Page 158

• Manufacturer Part Number: ATA6617-P3QW
• Description: MCU W/LIN TX/5V REG/WTCDG 38VQFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6617-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

158
Atmel ATA6616/ATA6617
Table 4-36
PWM mode.
Table 4-36.
Table 4-37
phase correct or the phase and frequency correct, PWM mode.
Table 4-37.
• Bit 3:2 – Reserved Bits
These bits are reserved for future use.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the count-
ing sequence of the counter, the source for maximum (TOP) counter value, and what type of
waveform generation to be used, see
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes.
147.).
Note:
Note:
OC1Ai
OC1Bi
OC1Ai
OC1Bi
0
1
1
1
1
0
1
1
1
1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
1. A special case occurs when OC1A/OC1B equals TOP and COM1A1/COM1B1 is set.
shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to the fast
this case the compare match is ignored, but the set or clear is done at TOP.
Mode” on page 149.
“Phase Correct PWM Mode” on page 151.
shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to the
COM1A1
COM1B1
COM1A1
COM1B1
Compare Output Mode, Fast PWM
Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
x
0
0
1
1
x
0
0
1
1
(1)
COM1A0
COM1B0
COM1A0
COM1B0
x
0
1
0
1
x
0
1
0
1
for more details.
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13=0: Normal port operation, OC1A/OC1B disconnected.
WGM13=1: Toggle OC1A on Compare Match, OC1B reserved.
Clear OC1A/OC1B on Compare Match
Set OC1A/OC1B at TOP
Set OC1A/OC1B on Compare Match
Clear OC1A/OC1B at TOP
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13=0: Normal port operation, OC1A/OC1B disconnected.
WGM13=1: Toggle OC1A on Compare Match, OC1B reserved.
Clear OC1A/OC1B on Compare Match when up-counting.
Set OC1A/OC1B on Compare Match when downcounting.
Set OC1A/OC1B on Compare Match when up-counting.
Clear OC1A/OC1B on Compare Match when downcounting.
Table
4-38. Modes of operation supported by the
(1)
for more details.
(See “Modes of Operation” on page
9132D–AUTO–12/10
See “Fast PWM
See