ATTINY25-15MZ Atmel, ATTINY25-15MZ Datasheet - Page 94

MCU AVR 2K FLASH 15MHZ 20-QFN

ATTINY25-15MZ

Manufacturer Part Number
ATTINY25-15MZ
Description
MCU AVR 2K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet

Specifications of ATTINY25-15MZ

Package / Case
20-QFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
6
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
UART, SPI, USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
4
Height
0.75 mm
Length
4 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
15.1
94
Timer/Counter1 Dead Time Prescaler register 1 - DTPS1
ATtiny25/45/85
The length of the counting period is user adjustable by selecting the dead time prescaler setting
in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register
consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM
output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x can
have different dead time periods. The dead time is adjusted as the number of prescaled dead
time generator clock cycles.
Figure 15-3. The Complementary Output Pair
The dead time prescaler register, DTPS1 is a 2-bit read/write register.
Bits 1 - 0 - DTPS1: Timer/Counter1 Dead Time Prescaler register 1
The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the
Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can
be generated. The Dead Time prescaler is controlled by two bits DTPS11..10 from the Dead
Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The
division factors are given in table 46..
Table 15-1.
Bit
$23 ($43)
Read/Write
Initial value
DTPS11
PWM1x
OC1x
OC1x
x = A or B
0
0
1
1
t
non-overlap / rising edge
Division factors of the Dead Time prescaler
R
7
0
DTPS10
0
1
0
1
R
6
0
Prescaler divides the T/C1 clock by
1x (no division)
2x
4x
8x
t
non-overlap / falling edge
5
R
0
R
4
0
R
3
0
R
2
0
DTPS11
R/W
1
0
DTPS10
R/W
0
0
7598H–AVR–07/09
DTPS1

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