ATTINY25-15MZ Atmel, ATTINY25-15MZ Datasheet - Page 33

• Manufacturer Part Number: ATTINY25-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-15MZ

• Package / Case: 20-QFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 6
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: UART, SPI, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Data Rom Size: 128 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 4
• Height: 0.75 mm
• Length: 4 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5
7.6
7598H–AVR–07/09
Limitations
Power Reduction Register
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details
Table 7-2.
Note:
BOD disable functionality has been implemented in the following devices, only:
The Power Reduction Register, PRR, provides a method to stop the clock to individualperipher-
als to reduce power consumption. The current state of the peripheral is frozenand the I/O
registers can not be read or written. Resources used by the peripheral when stopping the clock
will remain occupied, hence the peripheral should in most cases be disabled before stopping the
clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the
same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
• Bits 7, 6, 5, 4- Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 3- PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1
is enabled, operation will continue like before the shutdown.
Bit
Read/Write
Initial Value
Sleep Mode
Idle
ADC Noise
Reduction
Power-down
• ATtiny25, revision D, and newer
• ATtiny45, revision D, and newer
• ATtiny85, revision C, and newer
1. For INT0, only level interrupt.
.
.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
R
7
–
0
Active Clock Domains
R
6
0
-
X
X
X
R
5
0
-
X
R
4
0
-
Oscillators
X
X
PRTIM1
R/W
3
0
X
X
PRTIM0
X
(1)
(1)
R/W
2
0
“External Interrupts” on page 58
ATtiny25/45/85
Wake-up Sources
X
X
PRUSI
R/W
1
0
X
X
X
PRADC
R/W
0
0
X
X
X
PRR
X
X
X
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