ATTINY25-15MZ Atmel, ATTINY25-15MZ Datasheet - Page 82

MCU AVR 2K FLASH 15MHZ 20-QFN

ATTINY25-15MZ

Manufacturer Part Number
ATTINY25-15MZ
Description
MCU AVR 2K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet

Specifications of ATTINY25-15MZ

Package / Case
20-QFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
6
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
UART, SPI, USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
4
Height
0.75 mm
Length
4 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
82
ATtiny25/45/85
Figure 14-2. Timer/Counter 1 Synchronization Register Block Diagram.
Timer/Counter1 and the prescaler allow running the CPU from any clock source while the pres-
caler is operating on the fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock in the
asynchronous mode.
Note that the system clock frequency must be lower than one third of the PCK frequency. The
synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of
the PCK when the system clock is high. If the frequency of the system clock is too high, it is a
risk that data or control values are lost.
The following
PCKE
CK
PCK
SYNC
MODE
ASYNC
MODE
IO-registers
Figure 14-3
OCR1B
OCF1A
OCR1C
OCF1B
OCR1A
TCCR1
GTCCR
TCNT1
TOV1
1 - 2 PCK Delay
1/2 CK Delay
shows the block diagram for Timer/Counter1.
S
A
Input synchronization
registers
OCR1A_SI
OCR1B_SI
OCR1C_SI
TCCR1_SI
GTCCR_SI
TCNT1_SI
OCF1A_SI
OCF1B_SI
TOV1_SI
1 PCK Delay
1 CK Delay
S
A
8-BIT DATABUS
Timer/Counter1
TCNT1
~1 CK Delay
1 CK Delay
Output synchronization
registers
TCNT_SO
OCF1A_SO
OCF1B_SO
TOV1_SO
1/2 CK Delay
No Delay
7598H–AVR–07/09
TCNT1
OCF1A
OCF1B
TOV1

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