ATTINY25-15MZ Atmel, ATTINY25-15MZ Datasheet - Page 57
![MCU AVR 2K FLASH 15MHZ 20-QFN](/photos/30/99/309923/qfn-20_sml.jpg)
ATTINY25-15MZ
Manufacturer Part Number
ATTINY25-15MZ
Description
MCU AVR 2K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY25-15MZ.pdf
(196 pages)
Specifications of ATTINY25-15MZ
Package / Case
20-QFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
6
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
UART, SPI, USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
4
Height
0.75 mm
Length
4 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7598H–AVR–07/09
Table 10-4
shown in
Table 10-4.
Note:
Table 10-5.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
1. 1 when the Fuse is “0” (Programmed).
Figure 10-5 on page
PB5/RESET/
ADC0/PCINT5
RSTDISBL
1
RSTDISBL
debugWire Transmit
0
0
RSTDISBL
PCIE + ADC0D)
ADC0D
PCINT5 Input
RESET Input, ADC0 Input
PB2/SCK/ADC1/T0/
USCK/SCL/INT0/PCINT2
0
0
USI_TWO_WIRE
(USI_SCL_HOLD +
PORTB2) • DDB2
USI_TWO_WIRE • DDB2
0
USITC
PCINT2 • PCIE + ADC1D +
USISIE
ADC1D
T0/USCK/SCL/INT0/
PCINT2 Input
ADC1 Input
0
and
Overriding Signals for Alternate Functions in PB5..PB3
Overriding Signals for Alternate Functions in PB3..PB0
Table 10-5
(1)
(1)
(1)
• DWEN
• DWEN
+ (PCINT5 •
relate the alternate functions of Port B to the overriding signals
52.
(1)
(1)
PB4/ADC2/XTAL2/
OC1B/PCINT4
0
0
0
0
OC1B Enable
OC1B
0
PCINT4 • PCIE + ADC2D
ADC2D
PCINT4 Input
ADC2 Input
PB1/MISO/DO/AIN1/
OC1A/OC0B/PCINT1
0
0
0
0
OC0B Enable + OC1A
Enable +
USI_THREE_WIRE
OC0B + OC1A + DO
0
PCINT1 • PCIE + AIN1D
AIN1D
PCINT1 Input
Analog Comparator
Negative Input
ATtiny25/45/85
PB3/ADC3/XTAL1/
_OC1B/PCINT3
0
0
0
0
_OC1B Enable
_OC1B
0
PCINT3 • PCIE + ADC3D
ADC3D
PCINT3 Input
ADC3 Input
PB0/MOSI/DI/SDA/AIN0/AR
EF/_OC1A/OC0A/
PCINT0
0
0
USI_TWO_WIRE
(SDA + PORTBO) • DDB0
OC0A Enable + _OC1A
Enable + (USI_TWO_WIRE
• DDB0)
OC0A + _OC1A
0
PCINT0 • PCIE + AIN0D +
USISIE
AIN0D
DI/SDA/PCINT0 Input
Analog Comparator Positive
Input
57
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