ATMEGA8L-8AUR Atmel, ATMEGA8L-8AUR Datasheet - Page 72
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ATMEGA8L-8AUR
Manufacturer Part Number
ATMEGA8L-8AUR
Description
MCU AVR 8KB FLASH 8MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8L-8MU.pdf
(302 pages)
Specifications of ATMEGA8L-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
23
Interface Type
SPI/TWI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8L-8AUR
Manufacturer:
Atmel
Quantity:
3 915
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Timer/Counter
Register – TCNT0
Timer/Counter
Interrupt Mask
Register – TIMSK
Timer/Counter
Interrupt Flag Register
– TIFR
72
ATmega8(L)
Table 34. Clock Select Bit Description
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt Handling Vector. Alternatively, TOV0 is
cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow
Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
CS02
0
0
0
0
1
1
1
1
CS01
0
0
1
1
0
0
1
1
OCIE2
OCF2
R/W
R/W
R/W
7
0
7
0
7
0
CS00
0
1
0
1
0
1
0
1
TOIE2
TOV2
R/W
R/W
R/W
6
0
6
0
6
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on T0 pin. Clock on falling edge
External clock source on T0 pin. Clock on rising edge
TICIE1
ICF1
R/W
R/W
R/W
I/O
I/O
I/O
I/O
I/O
5
0
5
0
5
0
/(No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
OCIE1A
OCF1A
R/W
R/W
R/W
0
0
0
4
4
4
TCNT0[7:0]
OCIE1B
OCF1B
R/W
R/W
R/W
3
0
3
0
3
0
TOIE1
TOV1
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
–
0
–
TOIE0
TOV0
R/W
R/W
R/W
0
0
0
0
0
0
TCNT0
TIMSK
TIFR
2486Z–AVR–02/11
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