ATMEGA8L-8AUR Atmel, ATMEGA8L-8AUR Datasheet - Page 118

• Manufacturer Part Number: ATMEGA8L-8AUR
• Description: MCU AVR 8KB FLASH 8MHZ 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 32TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ATmega8(L)
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write a new value before the contents of the temporary register have been transferred to its
destination. Each of the three mentioned registers have their individual temporary register,
which means that, for example, writing to TCNT2 does not disturb an OCR2 write in
progress. To detect that a transfer to the destination register has taken place, the
Asynchronous Status Register – ASSR has been implemented
When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user
must wait until the written register has been updated if Timer/Counter2 is used to wake up
the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This
is particularly important if the Output Compare2 interrupt is used to wake up the device,
since the Output Compare function is disabled during writing to OCR2 or TCNT2. If the write
cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to
zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up
If Timer/Counter2 is used to wake the device up from Power-save mode, precautions must
be taken if the user wants to re-enter one of these modes: The interrupt logic needs one
TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less
than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the
user is in doubt whether the time before re-entering Power-save or Extended Standby mode
is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has
elapsed:
1. Write a value to TCCR2, TCNT2, or OCR2
2. Wait until the corresponding Update Busy Flag in ASSR returns to zero
3. Enter Power-save or Extended Standby mode
When the asynchronous operation is selected, the 32.768kHZ Oscillator for Timer/Counter2
is always running, except in Power-down and Standby modes. After a Power-up Reset or
Wake-up from Power-down or Standby mode, the user should be aware of the fact that this
Oscillator might take as long as one second to stabilize. The user is advised to wait for at
least one second before using Timer/Counter2 after Power-up or Wake-up from Power-down
or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost
after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-
up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin
Description of wake up from Power-save or Extended Standby mode when the timer is
clocked asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction
following SLEEP
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an
incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2
must be done through a register synchronized to the internal I/O clock domain.
Synchronization takes place for every rising TOSC1 edge. When waking up from Power-
save mode, and the I/O clock (clk
value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC
clock after waking up from Power-save mode is essentially unpredictable, as it depends on
the wake-up time. The recommended procedure for reading TCNT2 is thus as follows:
1. Write any value to either of the registers OCR2 or TCCR2
2. Wait for the corresponding Update Busy Flag to be cleared
3. Read TCNT2
I/O
) again becomes active, TCNT2 will read as the previous
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