ATMEGA8L-8AUR Atmel, ATMEGA8L-8AUR Datasheet - Page 209
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ATMEGA8L-8AUR
Manufacturer Part Number
ATMEGA8L-8AUR
Description
MCU AVR 8KB FLASH 8MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8L-8MU.pdf
(302 pages)
Specifications of ATMEGA8L-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
23
Interface Type
SPI/TWI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8L-8AUR
Manufacturer:
Atmel
Quantity:
3 915
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Performing Page
Erase by SPM
Filling the Temporary
Buffer (Page Loading)
Performing a Page
Write
Using the SPM
Interrupt
Consideration While
Updating BLS
Prevent Reading the
RWW Section During
Self-Programming
Setting the Boot
Loader Lock Bits by
SPM
2486Z–AVR–02/11
To execute page erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will
be ignored during this operation.
•
•
Note: If an interrupt occurs in the timed sequence, the four cycle access cannot be guaranteed.
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The con-
tent of PCWORD in the Z-register is used to address the data in the temporary page buffer. The
temporary buffer will auto-erase after a page write operation or by writing the RWWSRE bit in
SPMCR. It is also erased after a System Reset. Note that it is not possible to write more than
one time to each address without erasing the temporary buffer.
Note:
To execute page write, set up the address in the Z-pointer, write “X0000101” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
•
•
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SPMEN bit in SPMCR is cleared. This means that the interrupt can be used instead of polling
the SPMCR Register in software. When using the SPM interrupt, the Interrupt Vectors should be
moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is
blocked for reading. How to move the interrupts is described in
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
During Self-Programming (either page erase or page write), the RWW section is always blocked
for reading. The user software itself must prevent that this section is addressed during the self
programming operation. The RWWSB in the SPMCR will be set as long as the RWW section is
busy. During Self-Programming the Interrupt Vector table should be moved to the BLS as
described in
RWW section after the programming is completed, the user software must clear the RWWSB by
writing the RWWSRE. See
an example.
To set the Boot Loader Lock Bits, write the desired data to R0, write “X0001001” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The only accessible Lock Bits are
the Boot Lock Bits that may prevent the Application and Boot Loader section from any software
update by the MCU.
Bit
R0
Page Erase to the RWW section: The NRWW section can be read during the page erase
Page Erase to the NRWW section: The CPU is halted during the operation
Page Write to the RWW section: The NRWW section can be read during the page write
Page Write to the NRWW section: The CPU is halted during the operation
In order to ensure atomic operation, disable interrupts before writing to SPMCSR.
If the EEPROM is written in the middle of an SPM page Load operation, all data loaded will be lost
“Interrupts” on page
7
1
6
1
“Simple Assembly Code Example for a Boot Loader” on page 212
BLB12
5
46, or the interrupts must be disabled. Before addressing the
BLB11
4
BLB02
3
BLB01
2
“Interrupts” on page
1
1
ATmega8(L)
0
1
46.
209
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