ATMEGA8L-8AUR Atmel, ATMEGA8L-8AUR Datasheet - Page 171
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ATMEGA8L-8AUR
Manufacturer Part Number
ATMEGA8L-8AUR
Description
MCU AVR 8KB FLASH 8MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8L-8MU.pdf
(302 pages)
Specifications of ATMEGA8L-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
23
Interface Type
SPI/TWI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8L-8AUR
Manufacturer:
Atmel
Quantity:
3 915
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Transmission
Modes
Master Transmitter
Mode
2486Z–AVR–02/11
The TWI can operate in one of four major modes. These are named Master Transmitter (MT),
Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these
modes can be used in the same application. As an example, the TWI can use MT mode to write
data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters
are present in the system, some of these might transmit data to the TWI, and then SR mode
would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described
along with figures detailing data transmission in each of the modes. These figures contain the
following abbreviations:
S:
Rs:
R:
W:
A:
A:
Data: 8-bit data byte
P:
SLA: Slave Address
In
Flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler
bits masked to zero. At these points, actions must be taken by the application to continue or
complete the TWI transfer. The TWI transfer is suspended until the TWINT Flag is cleared by
software.
When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate soft-
ware action. For each status code, the required software action and details of the following serial
transfer are given in
are masked to zero in these tables.
In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver
(see
transmitted. The format of the following address packet determines whether Master Transmitter
or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if
SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section
assume that the prescaler bits are zero or are masked to zero.
Figure 79 on page 174
Figure 78 on page
START condition
REPEATED START condition
Read bit (high level at SDA)
Write bit (low level at SDA)
Acknowledge bit (low level at SDA)
Not acknowledge bit (high level at SDA)
STOP condition
Table 66 on page 173
172). In order to enter a Master mode, a START condition must be
to
Figure 85 on page
to
Table 69 on page
183, circles are used to indicate that the TWINT
182. Note that the prescaler bits
ATmega8(L)
171
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