ATMEGA8L-8MUR Atmel, ATMEGA8L-8MUR Datasheet
ATMEGA8L-8MUR
Specifications of ATMEGA8L-8MUR
Related parts for ATMEGA8L-8MUR
ATMEGA8L-8MUR Summary of contents
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... Standby • I/O and Packages – 23 Programmable I/O Lines – 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V (ATmega8L) – 4.5V - 5.5V (ATmega8) • Speed Grades – 8MHz (ATmega8L) – 16MHz (ATmega8) • Power Consumption at 4Mhz, 3V, 25°C – ...
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Pin Configurations ATmega8(L) 2 PDIP (RESET) PC6 1 28 PC5 (ADC5/SCL) (RXD) PD0 2 27 PC4 (ADC4/SDA) (TXD) PD1 3 26 PC3 (ADC3) (INT0) PD2 4 25 PC2 (ADC2) (INT1) PD3 5 24 PC1 (ADC1) (XCK/T0) PD4 6 23 PC0 ...
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... Overview The Atmel architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1MIPS per MHz, allowing the system designer to optimize power con- sumption versus processing speed. Block Diagram Figure 1. Block Diagram RESET VCC GND 2486Z–AVR–02/11 ® ...
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... Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications ...
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Pin Descriptions VCC Digital supply voltage. GND Ground. Port B (PB7..PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The XTAL1/XTAL2/TOSC1/ Port B output buffers have symmetrical drive characteristics with both high ...
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the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should externally connected to V nected to V AREF AREF is the analog reference pin for the A/D Converter. ...
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... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ...
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About Code This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compi- Examples lation. Be aware that not all ...
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... Atmel AVR CPU Core Introduction This section discusses the Atmel CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Figure 2. Block Diagram of the AVR MCU Architecture Overview In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data ...
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Flash Program memory. These added function registers are the 16-bit X-register, Y-register, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between ...
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... Arithmetic Logic The high-performance Atmel Unit – ALU purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementa- tions of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format ...
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Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates ...
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... AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit Read/Write Initial Value Instruction This section describes the general access timing concepts for instruction execution. The ® Atmel AVR Execution Timing source for the chip. No internal clock division is used. 2486Z–AVR–02/ ...
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... Figure 6. Single Cycle ALU Operation Register Operands Fetch ALU Operation Execute Reset and The Atmel Reset Vector each have a separate Program Vector in the Program memory space. All inter- Interrupt Handling rupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt ...
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt ...
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... Interrupt Response The interrupt execution response for all the enabled Atmel Time minimum. After four clock cycles, the Program Vector address for the actual interrupt handling routine is executed. During this 4-clock cycle period, the Program Counter is pushed onto the Stack ...
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... AVR ATmega8 This section describes the different memories in the Atmel ture has two main memory spaces, the Data memory and the Program Memory space. In Memories addition, the ATmega8 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
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... The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega8 are all accessible through all these addressing modes. The Register File is described in Figure 8. Data Memory Map ATmega8(L) 18 ® ® shows how the Atmel AVR SRAM Memory is organized. “General Purpose Register File” on page Register File ...
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Data Memory This section describes the general access timing concepts for internal memory access. The Access Times internal data SRAM access is performed in two clk Figure 9. On-chip Data SRAM Access Cycles EEPROM Data The ATmega8 contains 512bytes of ...
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... Read/Write Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the Atmel • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter- rupt when EEWE is cleared. • ...
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EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero 2. Wait until SPMEN in SPMCR becomes zero ...
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The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling inter- rupts globally) so that no interrupts will occur during execution of these ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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... I/O Memory The I/O space definition of the ATmega8 is shown in All Atmel are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... Flash Clock – clk The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- FLASH taneously with the CPU clock. 2486Z–AVR–02/11 presents the principal clock systems in the Atmel 33. The clock systems are detailed General I/O ADC Modules ...
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Asynchronous Timer The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly Clock – clk from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Coun- ASY ter as a real-time counter even when the ...
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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. The CKOPT Fuse selects between two different ...
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Table 5. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 Notes: Low-frequency To use a 32.768kHz watch crystal as the clock source for the device, the Low-frequency Crystal Oscillator must be ...
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By programming the CKOPT Fuse, the user can enable an internal 36pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor. Figure 12. External RC Configuration The Oscillator can operate in four different modes, ...
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... Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ±1% accuracy at any given V When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out ...
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Oscillator Calibration Bit Register – OSCCAL Read/Write Initial Value • Bits 7..0 – CAL7..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the Internal Oscillator to remove process vari- ations from the Oscillator frequency. During Reset, ...
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External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 13. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. By programming the CKOPT Fuse, ...
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Power Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- Management tion to the application’s requirements. and Sleep To ...
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Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue ...
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Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. ...
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Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume ...
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System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. If the program never enables an interrupt source, the Interrupt Vectors are not ...
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... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega8L and BODLEVEL = 0 for ATmega8. BODLEVEL = 1 is not appli- cable for ATmega8 DATA BUS ...
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Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in ...
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External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the ...
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Watchdog Reset When the Watchdog times out, it will generate a short reset pulse cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period t 43 for details on operation ...
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Internal Voltage ATmega8 features an internal bandgap reference. This reference is used for Brown-out Detec- Reference tion, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated ...
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Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical value at V controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Timer. The ...
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Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared ...
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Timed Sequences The sequence for changing the Watchdog Timer configuration differs slightly between the safety for Changing the levels. Separate procedures are described for each level. Assembly Code Example Configuration of the Watchdog WDT_off: Timer C Code Example void WDT_off(void) ...
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Interrupts This section describes the specifics of the interrupt handling performed by the ATmega8. For a general explanation of the AVR interrupt handling, refer to page 14. Interrupt Vectors in ATmega8 Table 18. Reset and Interrupt Vectors Vector No. 1 ...
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Table 19. Reset and Interrupt Vectors Placement BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega8 is: addressLabels Code $000 $001 $002 $003 $004 $005 $006 $007 ...
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When the BOOTRST Fuse is unprogrammed, the boot section size set to 2Kbytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt ...
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When the BOOTRST Fuse is programmed, the boot section size set to 2Kbytes, and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt ...
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...
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I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the ...
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Ports as General The ports are bi-directional I/O ports with optional internal pull-ups. Digital I/O a functional description of one I/O port pin, here generically called Pxn. Figure 22. General Digital I/O Pxn Note: Configuring the Pin Each port pin ...
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When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state ...
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It is clocked into the PINxn Register at the succeeding positive clock edge. As indi- cated by the two arrows t between ½ and 1-½ system clock period depending upon the time of assertion. When reading back a ...
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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...
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Unconnected pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs should ...
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Table 21 ure 25 on page 56 internally in the modules having the alternate function. Table 21. Generic Description of Overriding Signals for Alternate Functions Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO The following subsections ...
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Special Function IO Bit Register – SFIOR Read/Write Initial Value • Bit 2 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...
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SCK – Port B, Bit 5 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When ...
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Table 23. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: Table 24. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE ...
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Alternate Functions of The Port C pins with alternate functions are shown in Port C Table 25. Port C Pins Alternate Functions Port Pin PC6 PC5 PC4 PC3 PC2 PC1 PC0 The alternate pin configuration is as follows: • RESET ...
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ADC1 – Port C, Bit 1 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. • ADC0 – Port C, Bit 0 PC0 can also be used as ADC ...
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Alternate Functions of The Port D pins with alternate functions are shown in Port D Table 28. Port D Pins Alternate Functions Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • ...
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Table 29. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUO OOE OO PVOE PVO DIEOE DIEO DI AIO Table 30. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUO OOE OO PVOE PVO DIEOE DIEO DI ...
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Register Description for I/O Ports The Port B Data Bit Register – PORTB Read/Write Initial Value The Port B Data Bit Direction Register – DDRB Read/Write Initial Value The Port B Input Pins Bit Address – PINB Read/Write Initial Value ...
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External The external interrupts are triggered by the INT0, and INT1 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..1 pins are configured as outputs. This feature provides a Interrupts way of generating a software interrupt. ...
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Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre- sponding interrupt mask are set. The ...
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Bit 6 – INTF0: External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I- bit in SREG and the INT0 bit in GICR are set (one), the ...
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Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: Timer/Counter0 • Single Channel Counter • Frequency Generator • External Event Counter • 10-bit Clock Prescaler Overview A simplified block diagram of the 8-bit Timer/Counter ...
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Timer/Counter The Timer/Counter can be clocked by an internal or an external clock source. The clock source Clock Sources is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter Control ...
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Figure 28. Timer/Counter Timing Diagram, No Prescaling clk clk (clk TCNTn TOVn Figure 29 Figure 29. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Bit Read/Write Initial Value ...
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Table 34. Clock Select Bit Description CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as ...
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Timer/Counter0 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and and Timer/Counter0. Timer/Counter1 Prescalers Internal Clock Source The Timer/Counter can be clocked directly by the ...
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However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) ...
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The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: Timer/Counter1 • True 16-bit Design (that is, allows 16-bit PWM) • Two Independent Output Compare Units • Double ...
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Figure 32. 16-bit Timer/Counter Block Diagram Note: Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described ...
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The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture Pin (ICP1 the Analog Comparator pins (see “Analog Comparator” on page Canceler) for reducing the chance ...
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CPU, the High byte of the 16-bit register is copied into the tem- porary register in the same clock cycle as the Low byte is read. Not all 16-bit accesses uses the ...
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Assembly Code Example TIM16_ReadTCNT1: C Code Example unsigned int TIM16_ReadTCNT1( void ) { } Note: The assembly code example returns the TCNT1 value in the r17:r16 Register pair. 2486Z–AVR–02/11 (1) ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts ...
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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: ; Save Global Interrupt ...
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Figure 33. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk T 1 TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) con- taining the upper eight bits of the ...
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The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram ...
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The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture ...
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Figure 35 bit names indicates the device number ( for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are ...
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Force Output In non-PWM Waveform Generation modes, the match output of the comparator can be forced by Compare writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the OCF1x Flag or reload/clear the ...
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Figure 36. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC1x) from the waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or out- put) ...
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Compare Output Mode The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. and Waveform For all modes, setting the COM1x1 tells the waveform generator that no action on the Generation OC1x Register is ...
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Figure 37. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define ...
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OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In fast PWM mode the counter is incremented until the counter value matches either one of the ...
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Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively ...
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The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. Figure 39. Phase ...
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The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x ...
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Figure 40. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). ...
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TOP the output will be set to high for non- inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define ...
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TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 43. Timer/Counter Timing Diagram, no Prescaling (CTC ...
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Timer/Counter Register Description Timer/Counter 1 Bit Control Register A – TCCR1A Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for channel B The COM1A1:0 and ...
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Table 38 rect or the phase and frequency correct, PWM mode. Table 38. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COM1A1/ COM1B1 Note: • Bit 3 – FOC1A: Force Output Compare for ...
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Table 39. Waveform Generation Mode Bit Description (Continued) WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
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Table 40. Clock Select Bit Description CS12 external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as ...
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The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare Interrupt generate a waveform output on the OC1x pin. The Output ...
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Timer/Counter Bit Interrupt Flag Register (1) – TIFR Read/Write Initial Value Note: • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) ...
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Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: Timer/Counter2 • Single Channel Counter with PWM and • Clear Timer on Compare Match (Auto Reload) • Glitch-free, phase Correct Pulse Width Modulator (PWM) Asynchronous ...
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Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). ...
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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 46 shows a block diagram of the counter and its surrounding environment. Figure 46. Counter Unit Block Diagram Signal description (internal signals): count direction clear ...
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Output Compare The 8-bit comparator continuously compares TCNT2 with the Output Compare Register Unit (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If ...
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Force Output In non-PWM Waveform Generation modes, the match output of the comparator can be forced by Compare writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or reload/clear the ...
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Compare Match The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses Output Unit the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin ...
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Compare Output Mode The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. and Waveform For all modes, setting the COM21 tells the waveform generator that no action on the OC2 Generation Register is ...
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Clear Timer on In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manip- Compare Match (CTC) ulate the counter resolution. In CTC mode the counter is cleared to zero when the counter ...
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Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21 provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its sin- gle-slope operation. The counter counts ...
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The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer ...
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The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows ...
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Figure 53 Figure 53. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 54 Figure 54. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk clk (clk TCNTn OCRn OCFn 2486Z–AVR–02/11 shows the same timing data, ...
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Figure 55 Figure 55. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O clk clk (clk TCNTn (CTC) OCRn OCFn 8-bit Timer/Counter Register Description Timer/Counter Control Bit Register – TCCR2 Read/Write Initial Value • Bit ...
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Table 42. Waveform Generation Mode Bit Description Mode Note: • Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are ...
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Table 45 PWM mode. Table 45. Compare Output Mode, Phase Correct PWM Mode COM21 Note: • Bit 2:0 – CS22:0: Clock Select The three clock select bits select the clock source to be used by the ...
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Asynchronous Operation of the Timer/Counter Asynchronous Status Bit Register – ASSR Read/Write Initial Value • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clk written to one, Timer/Counter ...
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Each of the three mentioned registers have their individual temporary register, which means that, for example, writing to TCNT2 does not disturb an ...
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During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing ...
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Timer/Counter Figure 56. Prescaler for Timer/Counter2 Prescaler The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins ...
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Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8 and peripheral devices or between several AVR devices. The ATmega8 SPI includes Peripheral the following features: Interface – SPI • Full-duplex, Three-wire Synchronous Data Transfer • ...
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SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI ...
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The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi out ; Enable SPI ldi out ret SPI_SlaveReceive: ...
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SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the ...
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Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, ...
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Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled input and ...
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Figure 59. SPI Transfer Format with CPHA = 0 MSB first (DORD = 0) LSB first (DORD = 1) Figure 60. SPI Transfer Format with CPHA = 1 ATmega8(L) 128 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) ...
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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly-flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave ...
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The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, Transmitter and Receiver. Control Registers are shared by all units. The clock generation logic consists of synchronization logic for ...
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Figure 62. Clock Generation Logic, Block Diagram DDR_XCK Signal description: txclk rxclk xcki xcko fosc Internal Clock Internal clock generation is used for the asynchronous and the Synchronous Master modes of Generation – The operation. The description in this section ...
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Table 52. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal mode (U2X = 0) Asynchronous Double Speed Mode (U2X = 1) Synchronous Master Mode Note: BAUD Baud rate (in bits per second, bps) fOSC UBRR Contents of ...
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Figure 63. Synchronous Mode XCK Timing The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As ing XCK edge and sampled at falling XCK edge. If UCPOL is ...
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The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by ...
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Assembly Code Example USART_Init: C Code Example #define FOSC 1843200// Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) { } void USART_Init( unsigned int ubrr Note: More advanced initialization routines can be made that ...
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Data Transmission The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB – The USART Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den by the USART ...
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Sending Frames with If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB 9 Data Bits before the Low byte of the character is written to UDR. The following code ...
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UDR in order to clear UDRE or disable the Data Register empty Interrupt, otherwise a new inter- rupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) Flag bit is set one when the entire frame in the ...
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UDR will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } Note: ...
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The following code example shows a simple USART receive function that handles both 9-bit characters and the status bits. Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get status and ninth ...
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Receive Compete Flag The USART Receiver has one flag that indicates the Receiver state. and Interrupt The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread data ...
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Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXEN is set to zero) the Receiver will no longer override the ...
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The clock recovery logic then uses samples 8, 9 and 10 for Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid ...
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Asynchronous The operational range of the Receiver is dependent on the mismatch between the received bit Operational Range rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or ...
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The recommendations of the maximum Receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the Receivers Baud Rate error. The Receiver’s system ...
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Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. Accessing ...
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Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. How- ever, in most applications rarely necessary to read any of these registers. The read access is controlled by a ...
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USART Register Description USART I/O Data Register – UDR Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit ...
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Bit 4 – FE: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received (that is, when the first stop bit of the next character in the receive buffer ...
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Bit 3 – TXEN: Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero) will not ...
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Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...
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Bit 0 – UCPOL: Clock Polarity This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and ...
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Examples of Baud For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- Rate Setting chronous operation can be generated by using the UBRR settings in which yield an actual baud rate differing less than 0.5% ...
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Table 61. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 ...
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Table 62. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k 34 -0.8% ...
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Table 63. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 ...
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Two-wire Serial Interface Features • Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows up to 128 ...
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Electrical As depicted in Interconnection age through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI ...
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Figure 70. START, REPEATED START and STOP conditions SDA SCL Address Packet All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one Format READ/WRITE control bit and an acknowledge bit. If the ...
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Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while ...
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Multi-master Bus The TWI protocol allows bus systems with several masters. Special concerns have been taken Systems, in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. ...
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Figure 75. Arbitration Between Two Masters Synchronized Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It ...
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Overview of the The TWI module is comprised of several submodules, as shown in TWI Module in a thick line are accessible through the AVR data bus. Figure 76. Overview of the TWI Module SCL and SDA Pins These pins ...
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Bit Rate Generator This unit controls the period of SCL when operating in a Master mode. The SCL period is con- Unit trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status ...
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The TWINT Flag is set in the following situations: • After the TWI has transmitted a START/REPEATED START condition • After the TWI has transmitted SLA+R/W • After the TWI has transmitted an address byte • After the TWI has ...
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Bit 6 – TWEA: TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions ...
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Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. • Bits 1..0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 65. ...
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Bits 7..1 – TWA: TWI (Slave) Address Register These seven bits constitute the slave address of the TWI unit. • Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a ...
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The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted. If TWSR indicates otherwise, the applica- tion software might take some special action, like calling an error routine. Assuming ...
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Assembly Code Example ldi r16, (1<<TWINT)|(1<<TWSTA)| 1 (1<<TWEN) out TWCR, r16 wait1 r16,TWCR sbrs r16,TWINT rjmp wait1 in r16,TWSR 3 andi r16, 0xF8 cpi r16, START brne ERROR ldi r16, SLA_W out TWDR, r16 ldi r16, (1<<TWINT) | ...
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Transmission The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Modes Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As ...
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Figure 78. Data Transfer in Master Transmitter Mode A START condition is sent by writing the following value to TWCR: TWCR value TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit ...
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Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 66. Status codes for Master Transmitter Mode Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and ...
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Figure 79. Formats and States in the Master Transmitter Mode Successfull transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost ...
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Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter (see Figure format of the following address packet determines whether Master Transmitter or Master Receiver mode entered. If ...
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After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master ...
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Figure 81. Formats and States in the Master Receiver Mode Successfull reception from a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data byte Arbitration ...
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The upper 7 bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the ...
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Table 68. Status Codes for Slave Receiver Mode Status Code (TWSR) Status of the Two-wire Serial Bus Prescaler Bits and Two-wire Serial Interface are 0 Hardware 0x60 Own SLA+W has been received; ACK has been returned 0x68 Arbitration lost in ...
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Figure 83. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged Last data byte received is not acknowledged Arbitration lost as master and addressed as slave ...
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Slave Transmitter In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver Mode (see Figure zero or are masked to zero. Figure 84. Data Transfer in Slave Transmitter Mode To initiate the Slave Transmitter ...
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In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the ...
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Figure 85. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave (TWEA ...
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Combining Several In some cases, several TWI modes must be combined in order to complete the desired action. TWI Modes Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer ...
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Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on ...
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Analog The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin Comparator AIN1, the Analog Comparator Output, ...
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Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will ...
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Analog It is possible to select any of the ADC7..0 Comparator Comparator. The ADC multiplexer is used to select this input, and consequently the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit ...
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Analog-to- Digital Converter Features • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ±2 LSB Absolute Accuracy • 13µs - 260µs Conversion Time • kSPS at Maximum Resolution • 6 Multiplexed Single Ended Input Channels • 2 ...
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Figure 90. Analog to Digital Converter Block Schematic Operation AVCC AREF GND ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 The ADC converts an analog input voltage to a 10-bit digital value through successive approxi- mation. The minimum value represents ...
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If the result is left adjusted and no more than 8-bit precision is required sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the ...
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The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver- sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ...
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Figure 94. ADC Timing Diagram, Free Running Conversion Table 73. ADC Conversion Time Condition Extended conversion Normal conversions, single ended 2486Z–AVR–02/11 One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH MSB of Result ...
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Changing Channel The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary or Reference register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a ...
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ADC Noise The ADC features a noise canceler that enables conversion during sleep mode to reduce noise Canceler induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. ...
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Analog Noise Digital circuitry inside and outside the device generates EMI which might affect the accuracy of Canceling Techniques analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog ...
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Figure 97. Offset Error • Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB ...
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Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB Figure 99. Integral Non-linearity (INL) • Differential ...
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ADC Conversion After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Result Registers (ADCL, ADCH). For single ended conversion, the result is: where V Table 74 voltage minus one LSB. ADC ...
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Table 75. Input Channel Selections (Continued) MUX3..0 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC Control and Status Register A – Bit ADCSRA Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing this bit to ...