ATMEGA8L-8AUR Atmel, ATMEGA8L-8AUR Datasheet - Page 176

• Manufacturer Part Number: ATMEGA8L-8AUR
• Description: MCU AVR 8KB FLASH 8MHZ 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 32TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 67. Status codes for Master Receiver Mode
176
Status Code
(TWSR)
Prescaler Bits
are 0
0x08
0x10
0x38
0x40
0x48
0x50
0x58
ATmega8(L)
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
A START condition has been
transmitted
A repeated START condition
has been transmitted
Arbitration lost in SLA+R or NOT
ACK bit
SLA+R has been transmitted;
ACK has been received
SLA+R has been transmitted;
NOT ACK has been received
Data byte has been received;
ACK has been returned
Data byte has been received;
NOT ACK has been returned
After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the
same Slave again, or a new Slave without transmitting a STOP condition. Repeated START
enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver
mode without losing control over the bus.
To/from TWDR
Load SLA+R
Load SLA+R or
Load SLA+W
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action
Read data byte or
Read data byte
Read data byte or
Read data byte or
Read data byte
Application Software Response
STA
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
STO
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
To TWCR
TWINT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TWEA
X
X
X
X
X
0
1
X
X
X
0
1
X
X
X
Next Action Taken by TWI Hardware
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to Master Transmitter mode
Two-wire Serial Bus will be released and not addressed
Slave mode will be entered
A START condition will be transmitted when the bus
becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag will
be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag will
be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
2486Z–AVR–02/11