ATMEGA8L-8AUR Atmel, ATMEGA8L-8AUR Datasheet - Page 165
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ATMEGA8L-8AUR
Manufacturer Part Number
ATMEGA8L-8AUR
Description
MCU AVR 8KB FLASH 8MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8L-8MU.pdf
(302 pages)
Specifications of ATMEGA8L-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
23
Interface Type
SPI/TWI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8L-8AUR
Manufacturer:
Atmel
Quantity:
3 915
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TWI Register
Description
TWI Bit Rate Register
– TWBR
TWI Control Register –
TWCR
2486Z–AVR–02/11
The TWINT Flag is set in the following situations:
•
•
•
•
•
•
•
•
• Bits 7..0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See
Unit” on page 164
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT
Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-
cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag
starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta-
tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this
flag.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
After the TWI has transmitted a START/REPEATED START condition
After the TWI has transmitted SLA+R/W
After the TWI has transmitted an address byte
After the TWI has lost arbitration
After the TWI has been addressed by own slave address or general call
After the TWI has received a data byte
After a STOP or REPEATED START has been received while still addressed as a Slave
When a bus error has occurred due to an illegal START or STOP condition
TWBR7
TWINT
R/W
R/W
7
0
7
0
for calculating bit rates.
TWBR6
TWEA
R/W
R/W
6
0
6
0
TWBR5
TWSTA
R/W
R/W
5
0
5
0
TWBR4
TWSTO
R/W
R/W
4
0
4
0
TWBR3
TWWC
R/W
R
3
0
3
0
TWBR2
TWEN
R/W
R/W
2
0
2
0
TWBR1
R/W
R
1
0
1
–
0
TWBR0
TWIE
R/W
R/W
ATmega8(L)
0
0
0
0
“Bit Rate Generator
TWBR
TWCR
165
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