AT89LP214-20PU Atmel, AT89LP214-20PU Datasheet - Page 10

• Manufacturer Part Number: AT89LP214-20PU
• Description: MCU 8051 2K FLASH 20MHZ 14-PDIP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP214-20PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-DIP (0.300", 7.62mm)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8. Enhanced CPU
10
AT89LP213/214
The AT89LP213/214 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of stan-
dard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance
is due to two factors. First, the CPU fetches one instruction byte from the code memory every
clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions
in parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz. A sim-
ple example is shown in
The MCS-51 instruction set allows for instructions of variable length from 1 to 3 bytes. In a sin-
gle-clock-per-byte-fetch system this means each instruction takes at least as many clocks as it
has bytes to execute. The majority of instructions in the AT89LP213/214 follow this rule: the
instruction execution time in clock cycles equals the number of bytes per instruction with a
few exceptions. Branches and Calls require an additional cycle to compute the target address
and some other complex instructions require multiple cycles.
page 60
examples of 1- and 2-byte instructions.
Figure 8-1.
Figure 8-2.
Register Operand Fetch
ALU Operation Execute
Fetch Next Instruction
for more detailed information on individual instructions.
Total Execution Time
(n+1)
(n+2)
Result Write Back
Parallel Instruction Fetches and Executions
Single-cycle ALU Operation (Example: INC R0)
System Clock
n
System Clock
th
th
th
Instruction
Instruction
Instruction
Figure
8-1.
Fetch
T
T
n
1
Execute
Fetch
T
n+1
T
See “Instruction Set Summary” on
2
Figures 8-2 and 8-3
Execute
Fetch
T
n+2
T
3
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