MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 65

• Manufacturer Part Number: MC68HC908JL8CSPE
• Description: IC MCU 8K FLASH 8MHZ 32-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
5.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and memories are released from reset to allow
the reset vector sequence to occur.
At power-on, the following events occur:
Freescale Semiconductor
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A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables OSCOUT.
Internal clocks to the CPU and modules are held inactive for 4096 ICLK cycles to allow stabilization
of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared.
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
IRST
ICLK
RST
IAB
ILLEGAL ADDRESS RST
Figure 5-6. Sources of Internal Reset
ILLEGAL OPCODE RST
RST PULLED LOW BY MCU
Figure 5-5. Internal Reset Timing
COPRST
32 CYCLES
POR
LVI
INTERNAL RESET
32 CYCLES
VECTOR HIGH
Reset and System Initialization
65