MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 159

• Manufacturer Part Number: MC68HC908JL8CSPE
• Description: IC MCU 8K FLASH 8MHZ 32-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

DDRD[7:0] — Data Direction Register D Bits
When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0,
reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Address:
DDRD Bit
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
port D I/O logic.
Reset:
Read:
Write:
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
0
1
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
DDRD7
$0007
Bit 7
0
PTD Bit
Figure 11-11. Data Direction Register D (DDRD)
X
X
(1)
DDRD6
6
0
Table 11-4. Port D Pin Functions
I/O Pin Mode
RESET
Input, Hi-Z
Figure 11-12. Port D I/O Circuit
Output
DDRD5
5
0
(2)
Table 11-4
NOTE
Accesses to DDRD
DDRD4
DDRDx
PTDx
4
0
Read/Write
DDRD[7:0]
DDRD[7:0]
summarizes the operation of the port D pins.
DDRD3
3
0
Figure 11-12
DDRD2
2
0
PTD[7:0]
PTDPU[6:7]
Read
Pin
Accesses to PTD
To ADC, TIM1, SCI
DDRD1
1
0
shows the
PTD[7:0]
PTD[7:0]
Write
DDRD0
Bit 0
PTDx
0
(3)
Port D
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