MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 30

• Manufacturer Part Number: MC68HC908JL8CSPE
• Description: IC MCU 8K FLASH 8MHZ 32-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory
30
Addr.
$003C
$003D
$FE00 Break Status Register (BSR)
$FE01 Reset Status Register (RSR)
$FE02
$FE03
$003A
$003B
$003E
$003F
$0035
$0036
$0037
$0038
$0039
U = Unaffected
Note: Writing a logic 0 clears SBSW.
TIM2 Channel 0 Status
TIM2 Channel 1 Status
ADC Input Clock Register
ADC Status and Control
and Control Register
and Control Register
Register Name
ADC Data Register
Break Flag Control
TIM2 Channel 0
TIM2 Channel 0
TIM2 Channel 1
TIM2 Channel 1
Unimplemented
Unimplemented
Register High
Register High
Register Low
Register Low
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
(T2CH0H)
(T2CH1H)
(T2CH0L)
(T2CH1L)
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
(ADICLK)
Reserved
(T2SC0)
(T2SC1)
(ADSCR)
Register
Register
(BFCR)
(ADR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
POR:
CH0F
CH1F
COCO
ADIV2
BCFE
Bit15
Bit15
Bit 7
POR
X = Indeterminate
Bit7
Bit7
AD7
0
0
R
R
0
0
0
0
1
0
CH0IE
CH1IE
ADIV1
Bit14
Bit14
AIEN
Bit6
Bit6
AD6
PIN
R
R
R
6
0
0
0
0
0
MS0B
ADCO
ADIV0
Bit13
Bit13
COP
Bit5
Bit5
AD5
0
R
R
R
5
0
0
0
0
0
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
= Unimplemented
ADCH4
MS0A
MS1A
Bit12
Bit12
ILOP
Bit4
Bit4
AD4
R
R
R
4
0
0
1
0
0
0
ELS0B
ELS1B
ADCH3
Bit11
Bit11
ILAD
Bit3
Bit3
AD3
R
R
R
3
0
0
1
0
0
0
MODRST
ELS0A
ELS1A
ADCH2
Bit10
Bit10
Bit2
Bit2
AD2
R
R
R
R
2
0
0
1
0
0
0
Freescale Semiconductor
= Reserved
See note
ADCH1
SBSW
TOV0
TOV1
Bit9
Bit1
Bit9
Bit1
AD1
LVI
R
R
1
0
0
1
0
0
0
0
CH0MAX
CH1MAX
ADCH0
Bit 0
Bit8
Bit0
Bit8
Bit0
AD0
R
R
R
0
0
1
0
0
0
0