MC68HC908JL8CSPE Freescale Semiconductor, MC68HC908JL8CSPE Datasheet - Page 154

• Manufacturer Part Number: MC68HC908JL8CSPE
• Description: IC MCU 8K FLASH 8MHZ 32-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JL8CSPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-SDIP (0.400", 10.16mm)
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Input/Output (I/O) Ports
DDRA[7:0] — Data Direction Register A Bits
Figure 11-4
When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Table 11-2
154
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
PTAPUE
1. X = Don’t care.
2. Pin pulled to V
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance.
summarizes the operation of the port A pins.
Bit
shows the port A I/O logic.
X
1
0
Address:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Reset:
Read:
Write:
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
DDRA Bit
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
DDRA7
0
0
1
$0004
DD
Bit 7
0
by internal pull-up.
Figure 11-3. Data Direction Register A (DDRA)
PTA Bit
DDRA6
X
X
X
(1)
6
0
Table 11-2. Port A Pin Functions
RESET
Figure 11-4. Port A I/O Circuit
I/O Pin Mode
Input, Hi-Z
DDRA5
Input, V
5
0
Output
DD
NOTE
(2)
(4)
DDRA4
DDRAx
PTAx
4
0
Accesses to DDRA
Read/Write
DDRA3
DDRA[7:0]
DDRA[7:0]
DDRA[7:0]
3
0
DDRA2
2
0
PTAPUEx
PTA[7:0]
DDRA1
Read
Pin
Pin
Accesses to PTA
1
0
To KBI
Freescale Semiconductor
DDRA0
PTA[7:0]
PTA[7:0]
Bit 0
PTA[7:0]
PTAx
0
Write
(3)
(3)