Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 68
Z8F083ASJ020EG
Manufacturer Part Number
Z8F083ASJ020EG
Description
IC ENCORE XP MCU FLASH 8K 28SOIC
Manufacturer
Zilog
Series
Encore!®r
Datasheet
1.Z8F083ASJ020EG.pdf
(256 pages)
Specifications of Z8F083ASJ020EG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Other names
269-4558-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F083ASJ020EG
Manufacturer:
Zilog
Quantity:
363
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PS026308-1207
Caution:
Interrupt Vectors and Priority
Interrupt Assertion
•
•
Interrupts are globally disabled by any of the following actions:
•
•
•
•
•
•
•
•
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, level 2 is the second highest priority, and level 1 is the lowest priority. If all the
interrupts are enabled with identical interrupt priority (all as level 2 interrupts, for
example), the interrupt priority is assigned from highest to lowest as specified in
on page 54. Level 3 interrupts are always assigned higher priority than level 2 interrupts
and level 2 interrupts are assigned higher priority than level 1 interrupts. Within each
interrupt priority level (level 1, level 2, or level 3), priority is assigned as specified in
Table 31
oscillator fail trap, Watchdog oscillator fail trap, and illegal instruction trap always have
highest (level 3) priority.
Interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the
corresponding bit in the interrupt request register is cleared. Writing 0 to the
corresponding bit in the interrupt request register clears the interrupt request.
The coding style listed below that clears the bits in the interrupt request registers is Not
recommended. All incoming interrupts received between execution of the first
command and the final
Execution of an IRET (return from interrupt) instruction
Writing 1 to the IRQE bit in the interrupt control register
Execution of a DI (disable interrupt) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQE bit in the interrupt control register
Reset
Execution of a trap instruction
Illegal instruction Trap
Primary oscillator fail trap
Watchdog oscillator fail trap
on page 54, above. Reset, Watchdog Timer interrupt (if enabled), primary
Poor coding style that results in lost interrupt requests:
LDX r0, IRQ0
LDX
command are lost.
Z8 Encore!
Product Specification
®
Interrupt Controller
F083A Series
Table 31
LDX
56
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