Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 58

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Table 19. Port A–D Alternate Function Subregisters (PxAF)
Table 20. Port A–D Output Control Subregisters (PxOC)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
Caution:
POC7
R/W
AF7
If 02H in Port A–D Address Register, accessible through the Port A–D Control Register
If 03H in Port A–D Address Register, accessible through the Port A–D Control Register
7
7
0
Subregisters
pin, see
AF[7:0]—Port alternate function enabled
0 = The port pin is in NORMAL mode and the DDx bit in the Port A–D data direction
subregister determines the direction of the pin.
1 = The alternate function selected through alternate function set subregisters is enabled.
Port pin operation is controlled by the alternate function.
Port A–D Output Control Subregisters
The Port A–D output control subregister is accessed through the Port A–D control register
by writing
A–D output control subregisters to 1, configures the specified port pins for open-drain
operation. These subregisters affect the pins directly and, as a result, alternate functions
are also affected.
POC[7:0]—Port output control
These bits function independently of the alternate function bit and always disable the drains,
if set to 1.
GPIO Alternate Functions
Do not enable alternate functions for GPIO port pins for which there is no
associated alternate function. Failure to follow this guideline results in
unpredictable operation.
POC6
R/W
AF6
03H
6
6
0
on page 49
to the Port A–D address register. See
POC5
R/W
AF5
5
5
0
. T
o determine the alternate functions associated with each port
00H (Ports A–C); 01H (Port D)
POC4
R/W
AF4
on page 38.
4
4
0
R/W
POC3
R/W
AF3
3
3
0
Table
POC2
R/W
AF2
Z8 Encore!
20. Setting the bits in the Port
2
2
0
General Purpose Input/Output
Product Specification
POC1
R/W
AF1
1
1
0
®
F083A Series
POC0
R/W
AF0
0
0
0
46