Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 56

IC ENCORE XP MCU FLASH 8K 28SOIC

Z8F083ASJ020EG

Manufacturer Part Number
Z8F083ASJ020EG
Description
IC ENCORE XP MCU FLASH 8K 28SOIC
Manufacturer
Zilog
Series
Encore!®r
Datasheet

Specifications of Z8F083ASJ020EG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
Other names
269-4558-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8F083ASJ020EG
Manufacturer:
Zilog
Quantity:
363
Table 16. Port A–D GPIO Address Registers (PxADDR)
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
PADDR[7:0]
09H–FFH
00H
01H
02H
03H
04H
05H
06H
07H
08H
Port A–D Address Registers
Port A–D Control Registers
R/W
7
The Port A–D address registers select the GPIO port functionality accessible through the
Port A–D control registers. The Port A–D address and control registers combine to
provide access to all GPIO port controls (see
PADDR[7:0]—Port Address
The port address selects one of the subregisters accessible through the port control
register.
The Port A–D control registers set the GPIO port operation. The value in the
corresponding Port A–D address register determines, which subregister is read from or
written to by a Port A–D control register transaction. See
Port Control subregister accessible using the Port A–D Control Registers
No function. Provides some protection against accidental port reconfiguration.
Data direction
Alternate function
Output control (Open-Drain)
High drive enable
Stop Mode Recovery source enable.
Pull-up enable
Alternate function set 1
Alternate function set 2
No function
R/W
6
R/W
5
FD0H, FD4H, FD8H, FDCH
R/W
4
PADDR[7:0]
00H
Table
R/W
3
16).
Table 17
R/W
Z8 Encore!
2
General Purpose Input/Output
Product Specification
on page 45.
R/W
1
®
F083A Series
R/W
0
44

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