Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 147
Z8F083ASJ020EG
Manufacturer Part Number
Z8F083ASJ020EG
Description
IC ENCORE XP MCU FLASH 8K 28SOIC
Manufacturer
Zilog
Series
Encore!®r
Datasheet
1.Z8F083ASJ020EG.pdf
(256 pages)
Specifications of Z8F083ASJ020EG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Other names
269-4558-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F083ASJ020EG
Manufacturer:
Zilog
Quantity:
363
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PS026308-1207
Figure 19. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
DEBUG Mode
The operating characteristics of the devices in DEBUG mode are:
•
•
•
•
•
Entering DEBUG Mode
•
•
Exiting DEBUG Mode
The device exits DEBUG mode following any of these operations:
•
•
•
•
RS-232 TX
RS-232 RX
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute
specific instructions.
The system clock operates, unless the device is in STOP mode.
All enabled on-chip peripherals operate, unless the device is in STOP mode.
Automatically exits HALT mode.
Constantly refreshes the Watchdog Timer, if enabled.
The device enters DEBUG mode after the eZ8 CPU executes a BRK (Breakpoint)
instruction.
If the DBG pin is held low during the most recent clock cycle of system reset, the device
enters DEBUG mode on exiting system reset
Clearing the DBGMODE bit in the OCD control register to 0.
Power-On Reset.
Voltage Brownout reset.
Watchdog Timer reset.
Transceiver
RS-232
Open-Drain
Buffer
VDD
10KOhm
Z8 Encore!
DBG Pin
Product Specification
®
On-Chip Debugger
F083A Series
135
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