DSPIC30F2010-20I/SP Microchip Technology, DSPIC30F2010-20I/SP Datasheet - Page 197

• Manufacturer Part Number: DSPIC30F2010-20I/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20I/SP

• Program Memory Type: FLASH
• Program Memory Size: 12KB (4K x 24)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 20
• Data Ram Size: 512 B
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F2010-20I/SPG; DSPIC30F201020ISG; DSPIC30F201020ISG; DSPIC30F201020ISP

TimerQ (QEI Module) External Clock Timing
Timing Characteristics
Timing Diagrams
Timing Diagrams and Specifications
Timing Diagrams.See Timing Characteristics
Timing Requirements
 2004 Microchip Technology Inc.
Register Map............................................................... 65
Timer Prescaler........................................................... 64
Characteristics .......................................................... 166
A/D Conversion
Bandgap Start-up Time............................................. 163
CLKOUT and I/O....................................................... 160
External Clock........................................................... 157
I
I
Input Capture (CAPX) ............................................... 167
Motor Control PWM Module...................................... 169
Motor Control PWM Module Falult............................ 169
OC/PWM Module ...................................................... 168
Oscillator Start-up Timer ........................................... 161
Output Compare Module........................................... 167
Power-up Timer ........................................................ 161
QEI Module Index Pulse ........................................... 171
Reset......................................................................... 161
SPI Module
TimerQ (QEI Module) External Clock ....................... 166
Type A, B and C Timer External Clock ..................... 164
Watchdog Timer........................................................ 161
Center Aligned PWM .................................................. 85
Dead-Time .................................................................. 86
Edge Aligned PWM..................................................... 84
PWM Output ............................................................... 73
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
DC Characteristics - Internal RC Accuracy............... 159
A/D Conversion
Bandgap Start-up Time............................................. 163
Brown-out Reset ....................................................... 162
CLKOUT and I/O....................................................... 160
External Clock........................................................... 158
I
I
Input Capture ............................................................ 167
Motor Control PWM Module...................................... 169
Oscillator Start-up Timer ........................................... 162
Output Compare Module........................................... 167
Power-up Timer ........................................................ 162
2
2
2
2
C Bus Data
C Bus Start/Stop Bits
C Bus Data (Master Mode)..................................... 178
C Bus Data (Slave Mode)....................................... 180
10-Bit High-speed (CHPS = 01,
10-bit High-speed (CHPS = 01,
Master Mode ..................................................... 177
Slave Mode ....................................................... 179
Master Mode ..................................................... 177
Slave Mode ....................................................... 179
Master Mode (CKE = 0) .................................... 172
Master Mode (CKE = 1) .................................... 173
Slave Mode (CKE = 0) ...................................... 174
Slave Mode (CKE = 1) ...................................... 175
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
High-speed ....................................................... 185
SIMSAM = 0, ASAM = 0, SSRC = 000) .... 183
SIMSAM = 0, ASAM = 1,
SSRC = 111, SAMC = 00001) .................. 184
DD
).......................................... 126
DD
DD
), Case 1...................... 126
), Case 2...................... 126
Preliminary
Timing Specifications
U
UART
Unit ID Locations .............................................................. 119
Universal Asynchronous Receiver Transmitter. See UART.
W
Wake-up from Sleep ......................................................... 119
Wake-up from Sleep and Idle ............................................. 41
Watchdog Timer
Watchdog Timer (WDT)............................................ 119, 129
WWW, On-Line Support ....................................................... 4
QEI Module
Quadrature Decoder................................................. 170
Reset ........................................................................ 162
Simple OC/PWM Mode ............................................ 168
SPI Module
Type A Timer External Clock.................................... 164
Type B Timer External Clock.................................... 165
Watchdog Timer ....................................................... 162
PLL Clock ................................................................. 159
Address Detect Mode ............................................... 107
Auto Baud Support ................................................... 107
Baud Rate Generator ............................................... 107
Enabling and Setting Up UART ................................ 105
Loopback Mode ........................................................ 107
Module Overview...................................................... 103
Operation During CPU Sleep and Idle Modes.......... 108
Receiving Data ......................................................... 106
Reception Error Handling ......................................... 106
Transmitting Data ..................................................... 105
UART1 Register Map ............................................... 109
Timing Characteristics .............................................. 161
Timing Requirements ............................................... 162
Enabling and Disabling............................................. 129
Operation.................................................................. 129
External Clock .................................................. 166
Index Pulse....................................................... 171
Master Mode (CKE = 0).................................... 172
Master Mode (CKE = 1).................................... 173
Slave Mode (CKE = 0)...................................... 174
Slave Mode (CKE = 1)...................................... 176
Alternate I/O ..................................................... 105
Disabling........................................................... 105
Enabling ........................................................... 105
Setting Up Data, Parity and Stop Bit
In 8-bit or 9-bit Data Mode................................ 106
Interrupt ............................................................ 106
Receive Buffer (UxRCB)................................... 106
Framing Error (FERR) ...................................... 107
Idle Status ........................................................ 107
Parity Error (PERR) .......................................... 107
Receive Break .................................................. 107
Receive Buffer Overrun Error (OERR Bit) ........ 106
In 8-bit Data Mode ............................................ 105
In 9-bit Data Mode ............................................ 105
Interrupt ............................................................ 106
Transmit Buffer (UxTXB) .................................. 105
Selections................................................. 105
dsPIC30F2010
DS70118D-page 195