DSPIC30F2010-20I/SP Microchip Technology, DSPIC30F2010-20I/SP Datasheet

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... Microchip Technology Inc. dsPIC30F2010 Data Sheet 28-pin High Performance Digital Signal Controllers Preliminary DS70118D ...

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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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... Enhanced Flash 16-bit Digital Signal Controller Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual (DS70046) ...

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... This table provides a summary of the dsPIC30F2010 peripheral features. Other available devices in the dsPIC30F Motor Control and Power Conversion Family are shown for feature comparison. DS70118D-page 2 • Detects clock failure and switches to on-chip low power RC oscillator • Programmable code protection • ...

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... AN5/QEB/IC8/CN7/RB5 OSC1/CLKIN OSC2/CLKO/RC15  2004 Microchip Technology Inc. 1 MCLR REF +/CN2/RB0 REF -/CN3/RB1 26 PWM1L/RE0 4 PWM1H/RE1 PWM2L/RE2 6 PWM2H/RE3 23 7 PWM3L/RE4 PWM3H/RE5 21 9 OSC1/CLKI PGC/EMUC/U1RX/SDI1/SDA/RF2 18 12 PGD/EMUD/U1TX/SDO1/SCL/RF3 FLTA/INT0/SCK1/OCFA/RE8 14 15 EMUC2/OC1/IC1/INT1/RD0 1 21 PWM2L/RE2 2 20 PWM2H/RE3 3 19 PWM3L/RE4 dsPIC30F2010 4 PWM3H/RE5 PGC/EMUC/U1RX/SDI1/SDA/RF2 7 15 Preliminary dsPIC30F2010 DS70118D-page 3 ...

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... Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 CPU Architecture Overview.......................................................................................................................................................... 9 3.0 Memory Organization ................................................................................................................................................................. 19 4.0 Address Generator Units ............................................................................................................................................................ 31 5.0 Interrupts .................................................................................................................................................................................... 37 6.0 Flash Program Memory .............................................................................................................................................................. 43 7.0 Data EEPROM Memory ............................................................................................................................................................. 49 8.0 I/O Ports ..................................................................................................................................................................................... 53 9.0 Timer1 Module ........................................................................................................................................................................... 57 10.0 Timer2/3 Module ........................................................................................................................................................................ 61 11.0 Input Capture Module................................................................................................................................................................. 67 12.0 Output Compare Module ............................................................................................................................................................ 71 13 ...

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... Programmer’s Reference Manual (DS70030).  2004 Microchip Technology Inc. dsPIC30F2010 This document contains device specific information for the dsPIC30F2010 device. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) func- tionality within a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a device block diagram for the dsPIC30F2010 device ...

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... FIGURE 1-1: dsPIC30F2010 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH Program Counter Stack Address Latch Control Control Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch Instruction Decode & ...

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... ICD Tertiary Communication Channel clock input/output pin. ICD Quaternary Communication Channel data input/output pin. ICD Quaternary Communication Channel clock input/output pin. Capture inputs. The dsPIC30F2010 has 4 capture inputs. The inputs are numbered for consistency with the inputs on larger device variants. Quadrature Encoder Index Pulse input. ...

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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type RB0-RB5 I/O ST RC13-RC14 I/O ST RD0-RD1 I/O ST RE0-RE5, I/O ST RE8 RF2, RF3 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SS1 I ST SCL I/O ST SDA I/O ST SOSCO O — SOSCI I ST/CMOS ...

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... Programmer’s Reference Manual (DS70030). This document provides a summary dsPIC30F2010 CPU and peripheral function. For a complete description of this functionality, please refer to the dsPIC30F Family Reference Manual (DS70046). 2.1 Core Overview The core has a 24-bit instruction word. The Program Counter (PC bits wide with the Least Significant (LS) bit always clear (see Section 3 ...

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... Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (AccA and AccB), STATUS register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT), and Program Counter (PC) ...

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... DCOUNT 0 DOSTART DOEND 15 0 CORCON DC IPL2 IPL1 IPL0 SRL Preliminary dsPIC30F2010 PUSH.S Shadow DO Shadow Legend Working Registers Stack Pointer Limit Register AD0 Program Counter REPEAT Loop Counter DO Loop Counter DO Loop Start Address DO Loop End Address Core Configuration Register Z C Status Register ...

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... Divide Support The dsPIC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF – 16/16 signed fractional divide 2. DIV.sd – ...

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... EDAC MAC MAC MOVSAC MPY MPY.N MSC  2004 Microchip Technology Inc. dsPIC30F2010 The DSP engine has various options selected through various bits in the CPU Core Configuration Register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...

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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70118D-page 14 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill  2004 Microchip Technology Inc. ...

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... The OA and OB bits can also optionally generate an arithmetic warning trap when set and the correspond- ing overflow trap flag enable bit (OVATEN, OVBTEN) in the INTCON1 register (refer to Section 5.0) is set. This allows the user to take immediate action, for example, to correct system gain. Preliminary dsPIC30F2010 DS70118D-page 15 ...

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... The SA and SB bits are modified each time data passes through the adder/subtractor, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit sat- uration, or bit 39 for 40-bit saturation) and will be satu- rated (if saturation is enabled) ...

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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions.  2004 Microchip Technology Inc. dsPIC30F2010 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 15-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

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... NOTES: DS70118D-page 18 Preliminary  2004 Microchip Technology Inc. ...

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... Microchip Technology Inc. dsPIC30F2010 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F2010 GOTO Reset - Reset - Target Address Reserved Ext. Osc. Fail Trap Address Error Trap Stack Error Trap Arithmetic Warn ...

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... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using 0 PSVPAG Reg Program Space ...

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... Program Memory ‘Phantom’ Byte (Read as ‘0’).  2004 Microchip Technology Inc. dsPIC30F2010 A set of Table Instructions are provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the LS Word of the program address; ...

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... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MS BYTE) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 00000000 0x000006 Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...

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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses.  2004 Microchip Technology Inc. dsPIC30F2010 Program Space 0x0000 (1) PSVPAG 0x21 8 ...

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... FIGURE 3-6: DATA SPACE MEMORY MAP MS Byte Address 0x0001 SFR Space (Note) 0x07FF 0x0801 512 bytes 0x08FF 0x0901 SRAM Space 0x09FF 0x8001 Optionally Mapped into Program Memory 0xFFFF Note: Unimplemented SFR or SRAM locations read as ‘0’. DS70118D-page 24 16 bits MSB ...

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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W  2004 Microchip Technology Inc. dsPIC30F2010 SFR SPACE UNUSED Y SPACE UNUSED MAC Class Ops Read Only Indirect EA using W8, W9 ...

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... DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...

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... A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push.  2004 Microchip Technology Inc. dsPIC30F2010 There is a Stack Pointer Limit register (SPLIM) associ- ated with the stack pointer. SPLIM is uninitialized at Reset the case for the stack pointer, SPLIM<0> ...

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... DS70118D-page 28 Preliminary  2004 Microchip Technology Inc. ...

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... Microchip Technology Inc. dsPIC30F2010 Preliminary DS70118D-page 29 ...

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... NOTES: DS70118D-page 30 Preliminary  2004 Microchip Technology Inc. ...

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... The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the EA. The contents of Wn forms the EA post-modified (incremented or decremented constant value pre-modified (incremented or decremented signed constant value to form the EA. The sum of Wn and a literal forms the EA. Preliminary dsPIC30F2010 DS70118D-page 31 ...

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... MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 <function> Operand 2 where Operand 1 is always a working register (i.e., the Addressing mode can only be register direct), which is referred to as Wb. Operand 2 can register, fetched from data memory, or 5-bit literal. The result location can be either a W register or an address location ...

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... Bidirectional mode, (i.e., address bound- ary checks will be performed on both the lower and upper address boundaries).  2004 Microchip Technology Inc. dsPIC30F2010 4.2.1 START AND END ADDRESS The Modulo addressing scheme requires that a starting and an end address be specified and loaded ...

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... FIGURE 4-1: MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words DS70118D-page 34 MOV #0x1100,W0 MOV W0, XMODSRT ;set modulo start address MOV #0x1163,W0 MOV W0,MODEND ;set modulo end address MOV #0x8001,W0 MOV W0,MODCON ...

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... W register that has been designated as the bit-reversed pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Preliminary dsPIC30F2010 N bytes, addressing and bit-reversed should not be enabled DS70118D-page 35 ...

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... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 32768 16384 8192 4096 2048 1024 512 256 128 DS70118D-page 36 Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value Preliminary A0 Decimal ...

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... Manual (DS70046). For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual (DS70030). The dsPIC30F2010 has 44 interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt Vec- tor Table (IVT) and transferring the address contained in the interrupt vector to the program counter ...

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... For example, the PLVD (Low Voltage Detect) can be given a priority of 7. The INT0 (external interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority. DS70118D-page 38 TABLE 5-1: dsPIC30F2010 INTERRUPT VECTOR TABLE INT Vector Number Number ...

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... Trap Lockout: Occurrence of multiple Trap conditions simulta- neously will cause a Reset.  2004 Microchip Technology Inc. dsPIC30F2010 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1. They ...

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... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from our unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...

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... If an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor will wake-up from Sleep or Idle and begin execution of the Interrupt Service Routine (ISR) needed to process the interrupt request. Preliminary dsPIC30F2010 DS70118D-page 41 ...

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... DS70118D-page 42 Preliminary  2004 Microchip Technology Inc. ...

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... Addressing Using Table Instruction User/Configuration Space Select  2004 Microchip Technology Inc. dsPIC30F2010 6.2 Run Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...

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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary ...

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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP  2004 Microchip Technology Inc. dsPIC30F2010 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...

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... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...

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... Microchip Technology Inc. dsPIC30F2010 Preliminary DS70118D-page 47 ...

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... NOTES: DS70118D-page 48 Preliminary  2004 Microchip Technology Inc. ...

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... A TBLRD instruction reads a word at the current pro- gram word address. This example uses pointer to data EEPROM. The result is placed in register W4, as shown in Example 7-1. EXAMPLE 7-1: MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , TBLRDL [ Preliminary dsPIC30F2010 DATA EEPROM READ ; Init Pointer ; read data EEPROM DS70118D-page 49 ...

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... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in NVMCON register. ...

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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete  2004 Microchip Technology Inc. dsPIC30F2010 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...

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... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 [ W0]++ TBLWTL W2 , MOV #data2,W2 ...

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... I/O cell (pad) to which they are connected. Table 8-1 shows the formats of the registers for the shared ports, PORTB through PORTG. Output Multiplexers 1 Output Enable 0 1 Output Data Preliminary dsPIC30F2010 I/O Cell I/O Pad Input Data DS70118D-page 53 ...

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... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (out- ...

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... Microchip Technology Inc. dsPIC30F2010 Preliminary DS70118D-page 55 ...

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... NOTES: DS70118D-page 56 Preliminary  2004 Microchip Technology Inc. ...

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... Interrupt on 16-bit period register match or falling edge of external gate signal  2004 Microchip Technology Inc. dsPIC30F2010 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...

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... FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Reset 0 T1IF Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit TGATE (T1CON< ...

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... XTAL SOSCO pF 100K  2004 Microchip Technology Inc. dsPIC30F2010 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the period register, and is then reset to ‘0’. ...

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... DS70118D-page 60 Preliminary  2004 Microchip Technology Inc. ...

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... These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs.  2004 Microchip Technology Inc. dsPIC30F2010 For 32-bit timer/counter operation, Timer2 is the LS Word and Timer3 is the MS Word of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...

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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...

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... Comparator x 16 Reset 0 T3IF Event Flag 1 TGATE See NOTE Note: No External Clock Source is available for TIMER3. If TCS is set to ‘1’ then the TIMER3 module will not clock.  2004 Microchip Technology Inc. dsPIC30F2010 PR2 TMR2 Q D TGATE Q CK TON 1 X Gate 0 1 ...

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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...

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... Microchip Technology Inc. dsPIC30F2010 Preliminary DS70118D-page 65 ...

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... NOTES: DS70118D-page 66 Preliminary  2004 Microchip Technology Inc. ...

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... Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N.  2004 Microchip Technology Inc. dsPIC30F2010 The key operational features of the Input Capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • ...

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... Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • Capture every rising edge • Capture every 4th rising edge • Capture every 16th rising edge • Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits ICM< ...

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... Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode.  2004 Microchip Technology Inc. dsPIC30F2010 11.2.2 INPUT CAPTURE IN CPU IDLE MODE CPU Idle mode allows input capture module operation with full functionality. In the CPU Idle mode, the interrupt mode selected by the ICI< ...

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... DS70118D-page 70 Preliminary  2004 Microchip Technology Inc. ...

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... Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare. Set Flag bit OCxIF Output Logic 3 OCM<2:0> Mode Select OCTSEL T3P3_MATCH T2P2_MATCH Preliminary dsPIC30F2010 S Q OCx R Output Enable OCFA (for and 2) DS70118D-page 71 ...

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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers; Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the Output Compare module. 12.2 Simple Output Compare Match Mode When control bits OCM< ...

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... IFS0 Status register, and must be cleared in software. The interrupt is enabled via the respective timer interrupt enable bit (T2IE or T3IE), located in the IEC0 Control register. The output compare interrupt flag is never set during the PWM mode of operation. Preliminary dsPIC30F2010 DS70118D-page 73 ...

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... DS70118D-page 74 Preliminary  2004 Microchip Technology Inc. ...

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... Figure 13-1 depicts the Quadrature Encoder Interface block diagram. TQCKPS<1:0> TQCS QEIM<2:0> TQGATE CK Q 16-bit Up/Down Counter (POSCNT) 2 Quadrature Encoder Interface Logic Comparator/ Zero Detect 3 QEIM<2:0> Mode Select Max Count Register (MAXCNT) Preliminary dsPIC30F2010 bits QEIM<2:0> (QEICON<10:8>). 2 Prescaler 1, 8, 64, 256 QEIIF Event Flag Reset Equal DS70118D-page 75 ...

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... Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B, and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship ...

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... When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down.  2004 Microchip Technology Inc. dsPIC30F2010 In addition, control bit UPDN_SRC (QEICON<0>) determines whether the timer count direction state is based on the logic state, written into the UPDN control/ status bit (QEICON< ...

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... TIMER OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode and the QEI module is configured in the 16-bit Timer mode, the 16-bit timer will operate if the (QEICON<13> This bit defaults to a logic ‘0’ upon executing POR and BOR. For halting the timer module during the CPU Idle mode, QEISIDL should be set to ‘ ...

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... Microchip Technology Inc. dsPIC30F2010 Preliminary DS70118D-page 79 ...

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... NOTES: DS70118D-page 80 Preliminary  2004 Microchip Technology Inc. ...

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... Up to 16-bit resolution • ‘On-the-Fly’ PWM frequency changes • Edge and Center Aligned Output modes  2004 Microchip Technology Inc. dsPIC30F2010 • Single Pulse Generation mode • Interrupt support for asymmetrical updates in Center Aligned mode • Output override control for Electrically Commutative Motor (ECM) operation • ...

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... FIGURE 14-1: PWM BLOCK DIAGRAM PWMCON1 PWMCON2 DTCON1 FLTACON OVDCON PTMR Comparator PTPER PTPER Buffer PTCON Comparator SEVTDIR SEVTCMP PWM time base Note: Details of PWM Generator #1 and #2 not shown for clarity. DS70118D-page 82 PWM Enable and Mode SFRs Dead Time Control SFR ...

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... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR.  2004 Microchip Technology Inc. dsPIC30F2010 14.1.1 FREE RUNNING MODE In the Free Running mode, the PWM time base counts upwards until the value in the Time Base Period regis- ter (PTPER) is matched ...

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... DOUBLE UPDATE MODE In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR regis- ter is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double Update mode provides two additional func- tions to the user ...

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... PWM edge occurs in the beginning. Thus, the PWM resolution is effectively doubled.  2004 Microchip Technology Inc. dsPIC30F2010 14.5.1 DUTY CYCLE REGISTER BUFFERS The four PWM duty cycle registers are double buffered to allow glitchless updates of the PWM outputs. For ...

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... Dead Time Generators Dead time generation may be provided when any of the PWM I/O pin pairs are operating in the Complementary Output mode. The PWM outputs use Push-Pull drive circuits. Due to the inability of the power output devices to switch instantaneously, some amount of time must ...

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... PWMxH pin in the pair. Dead time insertion is still performed when PWM channels are overridden manually.  2004 Microchip Technology Inc. dsPIC30F2010 14.10.2 OVERRIDE SYNCHRONIZATION If the OSYNC bit in the PWMCON2 register is set, all output overrides performed via the OVDCON register are synchronized to the PWM time base ...

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... If all enable bits are cleared in the FLTACON register, then the FLTA input pin has no effect on the PWM mod- ule and the pin may be used as a general purpose inter- rupt or I/O pin. Note: The FLTA pin logic can operate indepen- dent of the PWM logic. If all the enable bits ...

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... CPU from Sleep mode. The PWM module generates an interrupt if either of the FLTA pins is driven low while in Sleep.  2004 Microchip Technology Inc. dsPIC30F2010 14.16 PWM Operation During CPU Idle Mode The PTCON SFR contains a PTSIDL control bit. This bit determines if the PWM module will continue to operate or stop when the device enters Idle mode ...

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... DS70118D-page 90 Preliminary  2004 Microchip Technology Inc. ...

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... Both the transmit buffer (SPIxTXB) and the receive buffer (SPIxRXB) are mapped to the same register address, SPIxBUF.  2004 Microchip Technology Inc. dsPIC30F2010 In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPIxBUF. The interrupt is generated at the middle of the transfer of the last bit ...

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... FIGURE 15-1: SPI BLOCK DIAGRAM Read SPIxBUF Receive SDIx bit0 SDOx SS & FSYNC Control SSx SCKx Note FIGURE 15-2: SPI MASTER/SLAVE CONNECTION SPI™ Master Serial Input Buffer (SPIxBUF) Shift Register (SPIxSR) MSb PROCESSOR 1 Note DS70118D-page 92 Internal Data Bus Write ...

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... Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MS bit, even if SSx had been de-asserted in the middle of a transmit/receive.  2004 Microchip Technology Inc. dsPIC30F2010 15.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut-down. If ...

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... DS70118D-page 94 Preliminary  2004 Microchip Technology Inc. ...

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... I2CRCV and an interrupt transmission, the I2CTRN is not double buffered. Note: Following a Restart condition in 10-bit mode, the user only needs to match the first 7-bit address. Preliminary dsPIC30F2010 2 C Standard and Fast mode specifica bus MODES 2 C operation are supported: 2 ...

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... FIGURE 16- BLOCK DIAGRAM Shift SCL Clock SDA Stop bit Detect Stop bit Generate Shift Clock DS70118D-page 96 I2CRCV I2CRSR LSB Addr_Match Match Detect I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down ...

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... I2CRCV is not full or I2COV is not set, I2CRSR is transferred to I2CRCV. ACK is sent on the ninth clock.  2004 Microchip Technology Inc. dsPIC30F2010 If the RBF flag is set, indicating that I2CRCV is still holding data from a previous operation (RBF = 1), then ACK is not sent; however, the interrupt pulse is gener- ated ...

Page 100

... Automatic Clock Stretch In the Slave modes, the module can synchronize buffer reads and write to the master device by clock stretching. 16.5.1 TRANSMIT CLOCK STRETCHING Both 10-bit and 7-bit Transmit modes implement clock stretching by asserting the SCLREL bit after the falling edge of the ninth clock if the TBF bit is cleared, indicat- ing the buffer is empty ...

Page 101

... Idle before the RCEN bit is set, other- wise the RCEN bit will be disregarded. The baud rate generator begins counting, and on each rollover, the state of the SCL pin toggles, and data is shifted in to the I2CRSR on the rising edge of each clock. Preliminary dsPIC30F2010 2 C bus will 2 C DS70118D-page 99 ...

Page 102

... BAUD RATE GENERATOR Master mode, the reload value for the BRG is located in the I2CBRG register. When the BRG is loaded with this value, the BRG counts down to 0 and stops until another reload has taken place. If clock arbi- tration is taking place, for instance, the BRG is reloaded when the SCL pin is sampled high ...

Page 103

... Microchip Technology Inc. dsPIC30F2010 Preliminary DS70118D-page 101 ...

Page 104

... NOTES: DS70118D-page 102 Preliminary  2004 Microchip Technology Inc. ...

Page 105

... Family Reference Manual (DS70046). This section describes the Universal Asynchronous Receiver/Transmitter Communications module. Note: Since dsPIC30F2010 devices have only one UART, all references to Ux... imply that only. FIGURE 17-1: UART TRANSMITTER BLOCK DIAGRAM Internal Data Bus ...

Page 106

... FIGURE 17-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · START bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic Note only. DS70118D-page 104 Internal Data Bus 16 Read Write UxRXREG Low Byte ...

Page 107

... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (Power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1).  2004 Microchip Technology Inc. dsPIC30F2010 17.3 Transmitting Data 17.3.1 TRANSMITTING IN 8-BIT DATA MODE ...

Page 108

... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the Transmit buffer to the Transmit Shift register (UxTSR) ...

Page 109

... Microchip Technology Inc. dsPIC30F2010 17.7 Loopback Mode Setting the LPBACK bit enables this special mode in which the UxTX pin is internally connected to the UxRX pin ...

Page 110

... UART Operation During CPU Sleep and Idle Modes 17.10.1 UART OPERATION DURING CPU SLEEP MODE When the device enters Sleep mode, all clock sources to the module are shutdown and stay at logic ‘0’. If entry into Sleep mode occurs while a transmission is in progress, then the transmission is aborted. The UxTX pin is driven to logic ‘ ...

Page 111

... Microchip Technology Inc. dsPIC30F2010 Preliminary DS70118D-page 109 ...

Page 112

... NOTES: DS70118D-page 110 Preliminary  2004 Microchip Technology Inc. ...

Page 113

... AN4 AN4 AN5 AN5 AN1  2004 Microchip Technology Inc. dsPIC30F2010 The A/D module has six 16-bit registers: • A/D Control Register1 (ADCON1) • A/D Control Register2 (ADCON2) • A/D Control Register3 (ADCON3) • A/D Input Select Register (ADCHS) • A/D Port Configuration Register (ADPCFG) • ...

Page 114

... A/D Result Buffer The module contains a 16-word dual port read-only buffer, called ADCBUF0...ADCBUFF, to buffer the A/D results. The RAM is 10-bits wide, but is read into different format 16-bit words. The contents of the sixteen A/D conversion result buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...

Page 115

... Example 18-1 shows a sample calculation for the ADCS<5:0> bits, assuming a device operating speed of 30 MIPS. EXAMPLE 18-1: AD (SAMC = Minimum T ADCS<5:0> cycles to Therefore, Set ADCS<5:0> Actual T AD wait is Preliminary dsPIC30F2010 AD . The source of the AD . A/D CONVERSION CLOCK = T * (0.5*(ADCS<5:0> +1 ADCS<5:0> – time ...

Page 116

... A/D Acquisition Requirements The analog input model of the 10-bit A/D converter is shown in Figure 18-2. The total sampling time for the A function of the internal amplifier settling time, device V DD and the holding capacitor charge time. For the A/D converter to meet its specified accuracy, ...

Page 117

... Each of the output formats translates to a 16-bit result on the data bus. Write data will always be in right justified (integer) format. d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Preliminary dsPIC30F2010 ...

Page 118

... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (out- ...

Page 119

... Microchip Technology Inc. dsPIC30F2010 Preliminary DS70118D-page 117 ...

Page 120

... NOTES: DS70118D-page 118 Preliminary  2004 Microchip Technology Inc. ...

Page 121

... In the Idle mode, the clock sources are still active, but the CPU is shut-off. The RC oscillator option saves system cost, while the LP crystal option saves power.  2004 Microchip Technology Inc. dsPIC30F2010 19.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...

Page 122

... TABLE 19-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2 PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2. 4x PLL enabled PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2. 8x PLL enabled PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2. 16x PLL enabled ...

Page 123

... FIGURE 19-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI  2004 Microchip Technology Inc. dsPIC30F2010 PLL F PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock Timer Switching and Control ...

Page 124

... Oscillator Configurations 19.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<1:0> configuration bits that select one of four oscillator groups. b) AND FPR<3:0> configuration bits that select one of 13 oscillator choices within the primary group. ...

Page 125

... PWRT expires. Note 1: OSC2 pin function is determined by the Primary (FPR<3:0>). 2: OSC1 pin cannot be used as an I/O pin even if the secondary oscillator or an internal clock source is selected at all times. Preliminary dsPIC30F2010 FRC TUNING FRC Frequency + 5.25% + 4.5% + 3.75% + 3.0% + 2.25 ...

Page 126

... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM configuration bits (Clock Switch and Monitor Selection bits) in the F configuration register. If the FSCM function is enabled, ...

Page 127

... Reset The dsPIC30F2010 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal operation) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Reset cause by trap lockup (TRAPR) h) Reset caused by illegal opcode using an ...

Page 128

... FIGURE 19-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 19-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 19-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...

Page 129

... The BOR voltage trip points indicated here are nominal values provided for design guidance only.  2004 Microchip Technology Inc. dsPIC30F2010 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device configuration bit values (FOS<1:0> and FPR< ...

Page 130

... Table 19-5 shows the Reset conditions for the RCON Register. Since the control bits within the RCON regis- ter are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 19-5: ...

Page 131

... If FSCM is not enabled, then the device will simply suspend execution of code until the clock is stable, and will remain in Sleep until the oscillator clock has started. Preliminary dsPIC30F2010 POR LOCK PWRT , T and T delays are (~ 10 µs) is applied. This is the smallest POR ...

Page 132

... All Resets will wake-up the processor from Sleep mode. Any Reset, other than POR, will set the Sleep status bit POR, the Sleep bit is cleared. If Watchdog Timer is enabled, then the processor will wake-up from Sleep mode upon WDT time-out. The Sleep and WDTO status bits are both set ...

Page 133

... Microchip Technology Inc. dsPIC30F2010 Preliminary DS70118D-page 131 ...

Page 134

... NOTES: DS70118D-page 132 Preliminary  2004 Microchip Technology Inc. ...

Page 135

... All instructions are a single word, except for certain double-word instructions, which were made double- word instructions so that all the required information is available in these 48-bits. In the second word, the 8 MSb’s are 0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Preliminary dsPIC30F2010 DS70118D-page 133 ...

Page 136

... Most single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (uncondi- ...

Page 137

... Y data space pre-fetch address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space pre-fetch destination register for DSP instructions ∈ {W4..W7} Wyd  2004 Microchip Technology Inc. dsPIC30F2010 Description Preliminary DS70118D-page 135 ...

Page 138

... TABLE 20-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...

Page 139

... Ws,Wd 28 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd  2004 Microchip Technology Inc. dsPIC30F2010 Description Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> ...

Page 140

... TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DISI DISI #lit14 30 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 31 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 34 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 35 EXCH EXCH Wns,Wnd 36 FBCL FBCL Ws,Wnd 37 FF1L FF1L ...

Page 141

... Ws,Wnd 70 SETM SETM f SETM WREG SETM Ws  2004 Microchip Technology Inc. dsPIC30F2010 Description Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd+1, Wnd} = unsigned(Wb) * ...

Page 142

... TABLE 20-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 71 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd 73 SUB SUB Acc SUB f SUB f,WREG SUB #lit10,Wn SUB Wb,Ws,Wd SUB Wb,#lit5,Wd 74 SUBB SUBB f SUBB f,WREG SUBB ...

Page 143

... CAN ® - PowerSmart - Analog  2004 Microchip Technology Inc. dsPIC30F2010 21.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...

Page 144

... MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...

Page 145

... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.  2004 Microchip Technology Inc. dsPIC30F2010 21.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...

Page 146

... PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It con- nects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices pins ...

Page 147

... Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices.  2004 Microchip Technology Inc. dsPIC30F2010 21.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...

Page 148

... NOTES: DS70118D-page 146 Preliminary  2004 Microchip Technology Inc. ...

Page 149

... Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific devices, please refer the the Family Cross Reference Table.  2004 Microchip Technology Inc. DD (except V and MCLR) ................................................... -0. (Note 1) ......................................................................................... 0V to +13.25V DD ) ..........................................................................................................± > ................................................................................................... ± ∑( pin, inducing currents greater than 80 mA, may cause latchup Preliminary dsPIC30F2010 DD + 0.3V) PP pin, rather DS70118D-page 147 ...

Page 150

... DC Characteristics TABLE 22-1: OPERATING MIPS VS. VOLTAGE DD V Range Temp Range 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C TABLE 22-2: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No ...

Page 151

... All I/O pins are configured as Inputs and pulled to V MCLR = WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating.  2004 Microchip Technology Inc. dsPIC30F2010 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ ...

Page 152

... TABLE 22-3: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) DD Operating Current (I ) DC27 — — DC27a 26 — DC27b — — DC27c — — DC27d 47 — DC27e — — DC27f — — DC28 — — DC28a 21 — DC28b — — ...

Page 153

... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. IDLE 2: Base I current is measured with Core off, Clock on and all modules turned off.  2004 Microchip Technology Inc. dsPIC30F2010 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...

Page 154

... TABLE 22-4: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. IDLE Idle Current (I ): Core OFF Clock ON Base Current DC47 — — DC47a 16.8 — DC47b — — DC47c — — DC47d 30.5 — DC47e — — DC47f — — DC48 — ...

Page 155

... LVD, BOR, WDT, etc. are all switched off. The ∆ current is the additional current consumed when the module is enabled. This current should added to the base I current.  2004 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial A Operating temperature -40° ...

Page 156

... TABLE 22-6: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No Input Low Voltage DI10 I/O pins: with Schmitt Trigger buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL IH V Input High Voltage ...

Page 157

... DD V – 0.7 — — TBD — — – 0.7 — — TBD — — — — 15 — — 50 — — 400 BO15 Power Up Time-out Preliminary dsPIC30F2010 ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA ...

Page 158

... TABLE 22-8: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param Symbol Characteristic No. (2) BOR BO10 V BOR Voltage V DD transition high to low BHYS BO15 V Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. ...

Page 159

... DC Spec Section 22.0. Load Condition 2 - for OSC2 Pin 464 Ω for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 Preliminary dsPIC30F2010 ≤ +85°C for Industrial A ≤ +125°C for Extended OS31 OS31 OS41 DS70118D-page 157 ...

Page 160

... TABLE 22-11: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OSC OS10 F External CLKIN Frequency (External clocks allowed only in EC mode) Oscillator Frequency OSC OSC OSC OS20 1/F CY OS25 T Instruction Cycle Time (2) OS30 TosL, External Clock in (OSC1) TosH High or Low Time ...

Page 161

... TBD — TBD % TBD — TBD % TBD — TBD % DD changes. Preliminary dsPIC30F2010 ≤ +85°C for Industrial ≤ +125°C for Extended Units Conditions MHz EC, XT modes with PLL MHz EC, XT modes with PLL µs % Measured over 100 ms period (3) (3) MIPS MIPS ...

Page 162

... FIGURE 22-4: CLKOUT AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 22-2 for load conditions. TABLE 22-15: CLKOUT AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. IO DO31 T R Port output rise time ...

Page 163

... DD V SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 22-2 for load conditions.  2004 Microchip Technology Inc. dsPIC30F2010 SY10 SY20 SY13 Preliminary SY13 DS70118D-page 161 ...

Page 164

... TABLE 22-16: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY10 TmcL MCLR Pulse Width (low) PWRT SY11 T Power-up Timer Period POR SY12 T Power On Reset Delay SY13 T IOZ I/O Hi-impedance from MCLR ...

Page 165

... T (1) (2) Min Typ Max Units — µs Preliminary dsPIC30F2010 BGAP V Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON< ...

Page 166

... FIGURE 22-7: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRX Note: “x” refers to Timer Type A or Timer Type B. Refer to Figure 22-2 for load conditions. TABLE 22-18: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...

Page 167

... TtxP TxCK Input Period Synchronous, CKEXTMRL TB20 T Delay from External TQCK Clock Edge to Timer Increment Note: Timer2 is Type B.  2004 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min Typ CY Synchronous, ...

Page 168

... FIGURE 22-8: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB POSCNT TABLE 22-20: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ10 TtQH TQCK High Time TQ11 TtQL TQCK Low Time TQ15 TtQP TQCP Input Period Synchronous, CKEXTMRL ...

Page 169

... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) (2) Min Typ Max — — Preliminary dsPIC30F2010 ≤ +85°C for Industrial ≤ +125°C for Extended Max Units Conditions — ns — ns — ns — ns — prescale value (1, 4, 16) ≤ ...

Page 170

... FIGURE 22-11: OC/PWM MODULE TIMING CHARACTERISTICS OCFA/OCFB OC15 OCx TABLE 22-23: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. FD OC15 T Fault Input to PWM I/O Change FLT OC20 T Fault Input Pulse Width Note 1: These parameters are characterized but not tested in manufacturing. ...

Page 171

... TBD TBD ns — TBD TBD ns — — TBD ns — — TBD ns Preliminary dsPIC30F2010 ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions -40°C to +85° -40°C to +85° -40°C to +85° -40°C to +85° -40°C to +85°C DD ...

Page 172

... FIGURE 22-14: QEA/QEB INPUT CHARACTERISTICS QEA (input) QEB (input) QEB Internal TABLE 22-25: QUADRATURE DECODER TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. QU TQ30 T L Quadrature Input Low Time QU TQ31 T H Quadrature Input High Time QU TQ35 T IN Quadrature Input Period TQ36 ...

Page 173

... Alignment of Index Pulses to QEA and QEB is shown for Position Counter reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but Index Pulse recognition occurs on falling edge.  2004 Microchip Technology Inc. dsPIC30F2010 TQ50 TQ55 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...

Page 174

... FIGURE 22-16: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SDOx SP31 SDIx MSb IN SP40 SP41 Note: Refer to Figure 22-2 for load conditions. TABLE 22-27: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...

Page 175

... X data input 20 — X data input 20 — Preliminary dsPIC30F2010 SP20 SP21 -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — — ns — — — ...

Page 176

... FIGURE 22-18: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) SP35 SDO X SDI SDI X SP40 Note: Refer to Figure 22-2 for load conditions. TABLE 22-29: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...

Page 177

... SP71 X SCK (CKP = 1) MSb X SDO X SDI SDI MSb IN SP41 SP40 Note: Refer to Figure 22-2 for load conditions.  2004 Microchip Technology Inc. SP70 SP20 SP35 SP20 SP52 BIT14 - - - - - -1 LSb SP30,SP31 BIT14 - - - -1 LSb IN Preliminary dsPIC30F2010 SP52 SP21 SP21 SP51 DS70118D-page 175 ...

Page 178

... TABLE 22-30: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TscL X SP70 SCK Input Low Time X SP71 TscH SCK Input High Time X SP20 TscF SCK Output Fall Time X SP21 TscR SCK Output Rise Time X SP30 TdoF SDO ...

Page 179

... I C BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 22-2 for load conditions.  2004 Microchip Technology Inc. dsPIC30F2010 IM11 IM10 IM26 IM25 IM40 Preliminary IM34 IM33 Stop Condition IM21 IM33 IM45 ...

Page 180

... TABLE 22-31 BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Param Symbol Characteristic No. LO SCL IM10 T : Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode IM11 SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode F SCL ...

Page 181

... IS30 SDA Start Condition 2 FIGURE 22-23 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out  2004 Microchip Technology Inc. dsPIC30F2010 IS33 IS11 IS10 IS26 IS25 IS40 Preliminary IS34 Stop Condition IS21 IS33 IS45 DS70118D-page 179 ...

Page 182

... TABLE 22-32 BUS DATA TIMING REQUIREMENTS (SLAVE MODE) AC CHARACTERISTICS Param Symbol Characteristic No. LO SCL IS10 T : Clock Low Time IS11 SCL Clock High Time F SCL IS20 T : SDA and SCL Fall Time IS21 SCL SDA and SCL Rise Time IS25 DAT Data Input ...

Page 183

... Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.  2004 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial A Operating temperature -40° ...

Page 184

... TABLE 22-33: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param Symbol Characteristic No. OFF AD24 E Offset Error OFF AD24A E Offset Error (2) AD25 — Monotonicity AD26 CMRR Common-Mode Rejection AD27 PSRR Power Supply Rejection Ratio AD28 CTLK Channel to Channel Crosstalk AD30 THD ...

Page 185

... Sampling starts after discharge period Software clears ADCON. SAMP to start conversion Sampling ends, conversion sequence starts Convert bit Convert bit Convert bit One T AD for end of conversion.  2004 Microchip Technology Inc. AD55 SAMP is described in Section 18.7. Preliminary dsPIC30F2010 AD55 DS70118D-page 183 ...

Page 186

... FIGURE 22-25: 10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001) AD50 ADCLK Instruction Execution BSF ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc SAMP T DONE ADIF ADRES(0) ADRES( Software sets ADCON. ADON to start AD operation Sampling starts after discharge period. ...

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... A/D Off to A/D On Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures.  2004 Microchip Technology Inc. dsPIC30F2010 Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...

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... NOTES: DS70118D-page 186 Preliminary  2004 Microchip Technology Inc. ...

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... For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2004 Microchip Technology Inc. dsPIC30F2010 Example dsPIC30F2010 -30I/MM 040700U Example dsPIC30F2010-30I/SP 0348017 Example dsPIC30F2010-30I/SO 0348017 Preliminary DS70118D-page 187 ...

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... Plastic Quad Flat No Lead Package 6x6x0.9 mm Body (QFN-S) – With 0.40 mm Contact Length (Saw Singulated) E TOP VIEW A1 Dimension Limits Number of Pins Pitch Overall Height Standoff Overall Width Exposed Pad Width Overall Length Exposed Pad Length Lead Width Lead Length ...

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... B1 .040 .053 .065 B .016 .019 .022 eB .320 .350 .430 α β Preliminary dsPIC30F2010 α MILLIMETERS MIN NOM MAX 28 2.54 3.56 3.81 4.06 3.18 3.30 3.43 0.38 7.62 7.87 8.26 6.99 7.24 7.49 34.16 34.67 35.18 3.18 3 ...

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... Plastic Small Outline – Wide, 300 mil (SOIC 45° c β Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width ...

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... Implementation ........................................................... 35 Modifier Values (table) ................................................ 36 Sequence Table (16-Entry)......................................... 36 Block Diagram PWM ........................................................................... 82 Block Diagrams 10-bit High Speed A/D Functional............................. 111 16-bit Timer1 Module .................................................. 58 DSP Engine ................................................................ 14 dsPIC30F2010 .............................................................. 6 External Power-on Reset Circuit............................... 127  2004 Microchip Technology Inc. dsPIC30F2010 .............................................................................. 96 Input Capture Mode.................................................... 67 Oscillator System...................................................... 121 Output Compare Mode ...

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... Reading....................................................................... 49 Write Verify ................................................................. 52 Writing ......................................................................... 51 Writing, Block .............................................................. 52 Writing, Word .............................................................. 51 DC Characteristics ............................................................ 148 BOR .......................................................................... 156 Brown-out Reset ....................................................... 155 I/O Pin Input Specifications ....................................... 154 I/O Pin Output Specifications .................................... 155 IDLE Idle Current (I ) .................................................... 151 Operating Current (I DD )............................................. 149 PD Power-Down Current (I ) ........................................ 153 Program and EEPROM............................................. 156 Temperature and Voltage Specifications ...

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... Initial Clock Source Selection ................................... 122 LP Oscillator Control ................................................. 123 Start-up Timer (OST) ................................................ 122 Oscillator Operating Modes Table .................................... 120 Oscillator Selection ........................................................... 119 2004 Microchip Technology Inc. dsPIC30F2010 Oscillator Start-up Timer Timing Characteristics .............................................. 161 Timing Requirements ............................................... 162 Output Compare Interrupts ................................................. 73 Output Compare Mode Register Map .............................................................. 74 Output Compare Module ...

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... PWM Duty Cycle Comparison Units ................................... 85 Duty Cycle Register Buffers ........................................ 85 PWM FLTA Pins.................................................................. 87 Enable Bits.................................................................. 87 Fault States ................................................................. 88 Modes ......................................................................... 88 Cycle-by-Cycle.................................................... 88 Latched ............................................................... 88 PWM Operation During CPU Idle Mode.............................. 89 PWM Operation During CPU Sleep Mode .......................... 89 PWM Output and Polarity Control ....................................... 87 Output Pin Control ...................................................... 87 PWM Output Override......................................................... 87 Complementary Output Mode ...

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... Input Capture ............................................................ 167 Motor Control PWM Module...................................... 169 Oscillator Start-up Timer ........................................... 162 Output Compare Module........................................... 167 Power-up Timer ........................................................ 162  2004 Microchip Technology Inc. dsPIC30F2010 QEI Module External Clock .................................................. 166 Index Pulse....................................................... 171 Quadrature Decoder................................................. 170 Reset ........................................................................ 162 Simple OC/PWM Mode ............................................ 168 SPI Module Master Mode (CKE = 0) ...

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... NOTES: DS70118D-page 196 Preliminary  2004 Microchip Technology Inc. ...

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... Microchip's development systems software products. Plus, this line provides information on how customers ® ® can receive the most current upgrade kits.The Hot Line or Microsoft Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Preliminary dsPIC30F2010 042003 DS70118D-page 197 ...

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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: dsPIC30F2010 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...