MA300012 Microchip Technology, MA300012 Datasheet
MA300012
Specifications of MA300012
Related parts for MA300012
MA300012 Summary of contents
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... Microchip Technology Inc. dsPIC30F Family Overview ® High-Performance 16-bit Digital Signal Controller DS70043F ...
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... PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Digital I/O: • programmable digital I/O pins • Wake-up/Interrupt-on-change pins • sink and source on all I/O pins © 2005 Microchip Technology Inc. High-Performance 16-bit ® On-Chip Flash, Data EEPROM and SRAM: • Flash program memory 144 Kbytes: - 10,000 erase/write cycles, min. (-40 to 85°C) - 100,000 erase/write cycles, typical • ...
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... DIP, 44-pin TQFP • 28-pin DIP (300 mil), 28-pin SOIC • 28-pin QFN • 18-pin DIP (300 mil), 18-pin SOIC Note: See Table 1-1, Table 1-2 and Table 1-3 for exact peripheral features per device. © 2005 Microchip Technology Inc. ...
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... Note 1: Maximum I/O pin count includes pins shared by the peripheral functions. 2: All 28- and 40-pin devices may be offered in ML packages in the future, depending on die size. 3: This device is not recommended for new designs. © 2005 Microchip Technology Inc. 1024 — 1024 ...
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... SOG, PG Custom ID (3 digits) or Engineering Sample (ES) Package TQFP 10x10 PT = TQFP 12x12 PF = TQFP 14x14 PG = DIP SPG= SPDIP SOG= SOIC ML = QFN 6x6 or 8x8 S = Die (Waffle Pack Die (Wafers) Speed MIPS MIPS T = Tape and Reel A,B,C… = Revision Level © 2005 Microchip Technology Inc. ...
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... Mapped DSP Engine Divide Control 16-bit ALU Legend: MCU/DSP X-Data Path DSP Y-Data Path Address Path © 2005 Microchip Technology Inc. dsPIC30F a wide variety of data addressing modes, together provide the dsPIC30F mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the dsPIC30F devices suitable for control applications ...
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... DCI Timers SPI2 X Data Bus Data Latch Data Latch Y Data X Data RAM RAM 16 (4 Kbytes) (4 Kbytes) Address Address Latch Latch RAGU Y AGU X WAGU Effective Address Reg Array 16 16 Divide Unit ALU<16> C™ I/O Ports UART1, UART2 © 2005 Microchip Technology Inc. ...
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... © 2005 Microchip Technology Inc. Note: The device depicted in Figure 4-1 is repre- sentative of this family. Other devices of the same family may vary in terms of number of pins and multiplexing of pin functions. Typically, smaller devices in the family contain a subset of the peripherals present in the device(s) shown here. ...
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... Reserved 000080 000084 Alternate Vector Table 0000FE 000100 User Flash Program Memory (48K instructions) 017FFE 018000 Reserved (Read 0’s) 7FEFFE 7FF000 Data EEPROM (4 Kbytes) 7FFFFE 800000 Reserved F7FFFE Device Configuration F80000 Registers F8000E F80010 Reserved FFFFFE © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. The dsPIC30F supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles ...
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... W14 can be referenced by any instruction in the same manner as all other W registers. The Stack Pointer always points to the first available free word and grows from lower addresses towards higher addresses. It pre-decrements for stack pops (reads) and post-increments for stack pushes (writes). © 2005 Microchip Technology Inc. ...
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... Registers 39 DSP ACCA Accumulators ACCB TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2005 Microchip Technology Inc W0/WREG W10 W11 W12/MAC Offset W13/MAC Write Back W14/Frame Pointer W15*/Stack Pointer SPLIM Program Space Visibility Page Address 15 ...
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... All word accesses must be aligned to an even address. Misaligned word data fetches are not supported. Should a misaligned read or write be attempted, a trap will then be executed, allowing the system and/or user to examine the machine state prior to execution of the address fault. © 2005 Microchip Technology Inc. with ...
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... FIGURE 5-3: SAMPLE DATA SPACE MEMORY MAP 2 Kbyte SFR Space 8 Kbyte SRAM Space 8 Kbyte SRAM boundary Optionally Mapped into Program Memory © 2005 Microchip Technology Inc. MS Byte 16-bits Address MSB LSB 0x0001 SFR Space 0x07FF 0x0801 X Data RAM (X) 0x17FF 0x1801 Y Data RAM (Y) ...
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... Data space write saturation ensures that the data in the accumulator is written back accurately even when rounding is performed. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word (lsb) is simply discarded. © 2005 Microchip Technology Inc. ...
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... FIGURE 5-4: DSP ENGINE BLOCK DIAGRAM 40 © 2005 Microchip Technology Inc. 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler Operand Latches 16 16 To/From W Array dsPIC30F Round u r Logic Enable 16 Zero Backfill DS70043F-page 15 ...
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... OC4 – Output Compare 4 0x0000BE T4 – Timer4 0x0000C0 T5 – Timer5 0x0000C2 INT2 – External Interrupt 2 0x0000C4 U2RX – UART2 Receiver 0x0000C6 U2TX – UART2 Transmitter 0x0000C8 SPI2 0x0000CA CAN1 the Peripheral module, which Interrupt Source © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. AIVT Address 0x0000CC IC3 – Input Capture 3 0x0000CE IC4 – ...
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... AIVT Address 0x000004 0x000084 0x000006 0x000086 0x000008 0x000088 0x00000A 0x00008A 0x00000C 0x00008C 0x00000E 0x00008E 0x000010 0x000090 0x000012 0x000092 Trap Source Reserved Oscillator Failure Address Error Stack Error Arithmetic Error Reserved Reserved Reserved © 2005 Microchip Technology Inc. ...
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... A Clock Control register (OSCCON) • Nonvolatile Configuration bits for main oscillator selection. A simplified block diagram of the oscillator system is shown in Figure 7-1. © 2005 Microchip Technology Inc. dsPIC30F 7.2 Power-On Reset When a supply voltage is applied to the device, a Power-on Reset is generated. A new Power-on Reset ...
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... Power-On Reset (POR), Brown-Out Reset (BOR) and wake-up from Sleep). The oscillator start-up timer is applied to the LP oscillator, XT, XTL and HS modes (upon wake-up from Sleep, POR and BOR) for the primary oscillator. Programmable OSC CY Clock Divider To Timer1 © 2005 Microchip Technology Inc. ...
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... The Trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail trap vector. © 2005 Microchip Technology Inc. 7.8 Reset System The Reset system combines all Reset sources and controls the device Master Reset signal ...
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... The voltage is software programmable to any of 16 values, or can be obtained from an external pin (LVDIN). DS70043F-page 22 FIGURE 8-1: External LVD by the Input pin V DD LVDIN LVDEN Internally Generated Reference Voltage LVD MODULE BLOCK DIAGRAM 4 LVDL<3.0> + LVDIF - © 2005 Microchip Technology Inc. ...
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... The processor exits (wakes up) from Sleep on one of these events: • Any interrupt source that is individually enabled. • Any form of device Reset. • A WDT time-out. © 2005 Microchip Technology Inc. dsPIC30F 8.3.2 IDLE MODE When the device enters Idle mode: • CPU stops executing instructions. ...
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... Ability to convert during CPU Sleep and Idle modes • Conversion start can be manual or synchronized with trigger sources (Automatic, Timer3, External Interrupt) • 16-word deep memory-mapped result buffer: - Lower and upper half of buffer can be filled on alternate conversions - pins available REF - pins available REF © 2005 Microchip Technology Inc. ...
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... Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI © 2005 Microchip Technology Inc. Further, the following operational characteristics are supported: • Timer gated by external pulse • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling ...
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... The 6-output MCPWM module is useful for single or 3-phase power application, while the 8 MCPWM can support 4-phase motor applications. The 8-output MCPWM (Figure 9-2) also provides increased flexibility in an application because it supports two fault pins and two programmable dead times. © 2005 Microchip Technology Inc. ...
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... PTCON Comparator SEVTDIR SEVTCMP PWM time base Note: Details of PWM Generator #1, #2 and #3 not shown for clarity. © 2005 Microchip Technology Inc. PWM Enable and Mode SFRs Dead-Time Control SFRs Fault Pin Control SFRs PWM Manual Control SFR PWM Generator #4 PDC4 Buffer ...
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... Count direction status • X2 and X4 count resolution • Two modes of position counter reset • General Purpose16-bit Timer/Counter mode • Interrupts generated by QEI or counter events PWM Frequency* 915 Hz 29.3 KHz 610 Hz 39.1 KHz 305 Hz 39.1 KHz 153 Hz 39.1 KHz © 2005 Microchip Technology Inc. ...
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... Det Programmable QEA Digital Filter UPDN_SRC QEICON<11> Programmable QEB Digital Filter Programmable INDX Digital Filter 3 PCDOUT Existing Pin Logic 0 UPDN Up/Down 1 © 2005 Microchip Technology Inc. TQCS QEIM<2:0> TQGATE CK 16-bit Up/Down Counter (POSCNT) 2 Quadrature Encoder Interface Logic Comparator/ Zero Detect 3 QEIM<2:0> ...
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... DCI can support time slots in a data frame, for a maximum frame size of 256 bits. There are control bits for each time slot in the data frame that determine whether the DCI will transmit/receive during the time slot. © 2005 Microchip Technology Inc. ...
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... Synchronization mode is also included for support of voice band codecs. Four pins make up the serial interface: SDI, serial data input; SDO, serial data output; SCK, shift clock input or output; SS, active low slave select, which also serves © 2005 Microchip Technology Inc. BCG Control Bits Sample Rate /4 Generator ...
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... Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the receive registers. © 2005 Microchip Technology Inc. ...
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... Port register provides the I/O pin logic state, while writes to the Port register write the data to the port Data Latch register. © 2005 Microchip Technology Inc. dsPIC30F I/O port pins have latch bits (Port Latch register). This register, when read, yields the contents of the I/O latch, ...
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... CALL, DO and GOTO Table 10-3 instructions, which are flow instructions listed in Table 10-4 Table 10-9. These instructions require two words of memory because their opcodes embed large literal Table 10-5 operands. Table 10-6 Table 10-7 Table 10-8 Table 10-9 © 2005 Microchip Technology Inc. ...
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... Source Addressing mode and working register for X data bus pre-fetch Wx Destination working register for X data bus pre-fetch Wxd Source Addressing mode and working register for Y data bus pre-fetch Wy Destination working register for Y data bus pre-fetch Wyd © 2005 Microchip Technology Inc. dsPIC30F Description DS70043F-page 35 ...
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... Move Wns to [Wd + signed 10-bit offset] Move Move double Ws to Wnd:Wnd + 1 Move double Wns:Wns + byte or nibble swap Wn Read high program word to Wd Read low program word to Wd Write Ws to high program word Write Ws to low program word Words Cycles © 2005 Microchip Technology Inc. ...
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... SUBR f {,WREG} SUBR Wb,#lit5,Wd SUBR Wb,Ws,Wd ZE Ws,Wnd * Divide instructions are interruptible on a cycle-by-cycle basis. Also, divide instructions must be accompanied by a REPEAT instruction, which adds 1 extra cycle. © 2005 Microchip Technology Inc. Description Destination = f + WREG Wn = lit10 + lit5 Destination = f + WREG + ( lit10 + lit5 + ( ( decimal adjust Wn Destination = f – ...
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... Destination = f .AND. WREG Wn = lit10 .AND .AND. lit5 .AND 0x0000 WREG = 0x0000 Wd = 0x0000 Destination = Destination = f .IOR. WREG Wn = lit10 .IOR .IOR. lit5 .IOR. Ws Destination = 0xFFFF WREG = 0xFFFF Wd = 0xFFFF Destination = f .XOR. WREG Wn = lit10 .XOR .XOR. lit5 .XOR. Ws Words Cycles © 2005 Microchip Technology Inc. ...
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... FF1L Ws,Wnd FF1R Ws,Wnd Note: Bit positions are specified by bit4 (0:15) for word operations. © 2005 Microchip Technology Inc. Description Destination = arithmetic right shift arithmetic right shift Ws Wnd = arithmetic right shift Wb by lit4 Wnd = arithmetic right shift Wb by Wns Destination = logical right shift f ...
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... Bit positions are specified by bit4 (0:15) for word operations. 2: Conditional skip instructions execute in 1 cycle if the skip is not taken, 2 cycles if the skip is taken over a one-word instruction and 3 cycles if the skip is taken over a two-word instruction. DS70043F-page 40 Description © 2005 Microchip Technology Inc. Words Cycles ...
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... Note 1: Conditional branch instructions execute in 1 cycle if the branch is not taken cycles if the branch is taken. 2: RETURN normally executes in 3 cycles. However, it executes in 2 cycles if an interrupt is pending. © 2005 Microchip Technology Inc. Description Branch unconditionally Computed branch Branch if Carry (no Borrow) Branch if greater than or equal ...
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... Multiply Acc Square to Acc -(Multiply Wn by Wm) to Acc Multiply and subtract from Acc Negate Acc Store Acc Store rounded Acc Arithmetic shift Acc by Slit6 Arithmetic shift Acc by (Wn) Subtract accumulators Words Cycles Words Cycles Words Cycles © 2005 Microchip Technology Inc. ...
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... Socket Module for 64L TQFP Devices ( mm) Socket Module for 80L TQFP Devices ( mm) * List Prices are subject to change without notice. Visit www.microchip.com for the latest information. © 2005 Microchip Technology Inc. party tools manufacturers for additional dsPIC30F device support. Table 11-1 lists development tools that support the dsPIC30F family ...
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... The ability to use the MPLAB IDE with multiple development and debugging targets provides easy transition from the cost effective simulator to MPLAB ICD full featured emulator with minimal retraining. © 2005 Microchip Technology Inc. Set break/trace points with a click of the mouse Simply move your mouse over a variable to view or modify ...
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... Besides modeling the behavior of the CPU, MPLAB SIM 30 also supports the following peripherals: • Timers • Input Capture • 12-bit ADC • 10-bit ADC © 2005 Microchip Technology Inc. dsPIC30F • Motor Control PWM • UART • I/O Ports • Program Flash and Data EEPROM 11 ...
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... MPLAB C30 Compiler/Linker/ Librarian The Microchip Technology MPLAB C30 provides C language support for the dsPIC30F family. This C compiler is a fully ANSI compliant product with standard libraries highly optimizing for the dsPIC30F family and takes advantage of many dsPIC30F architecture specific features to help you generate very efficient software code ...
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... Some device resources required (RAM and 2 pins) FIGURE 11-4: MPLAB ICD 2 IN-CIRCUIT DEBUGGER © 2005 Microchip Technology Inc. 11.7 MPLAB ICE 4000 In-Circuit Emulator The MPLAB ICE 4000 In-Circuit Emulator gives you a complete hardware design tool for dsPIC30F devices. ...
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... Large easy-to-read display • Field upgradeable firmware allows quick new device support • Secure Digital (SD) and Multimedia Card (MMC) external memory support • Buzzer notification for noisy environments FIGURE 11-6: production MPLAB PM3 DEVICE PROGRAMMER © 2005 Microchip Technology Inc. ...
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... C Compiler for dsPIC30F C Compiler C Compiler for dsPIC30F with IDE with IDE * Prices are subject to change without notice © 2005 Microchip Technology Inc. Table 12-1 summarizes dsPIC30F software tools and libraries. Microchip also provides value added services such as skilled/certified technical application contacts, reference designs and hardware and software developers ...
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... Comparison, integer and floating-point conversions (1)(2) 5250 4 (1)(3) 122 124 109 361 385 492 © 2005 Microchip Technology Inc. ...
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... Predefined constants in the C include files eliminate the need to refer to the details and structure of every Special Function Register while initializing peripherals or checking Status bits. © 2005 Microchip Technology Inc. dsPIC30F 12.3 DSP Algorithm Library The free DSP library supports multiple filtering, convolution, vector and matrix functions ...
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... Data dsPICworks Analysis and DSP Software © 2005 Microchip Technology Inc. ...
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... MPLAB workspace. © 2005 Microchip Technology Inc. 12.5 Digital Filter Design Software Utility The Digital Filter Design tool for the dsPIC30F 16-bit Digital Signal Controllers makes designing, analyzing and implementing Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) digital filters easy through a menu-driven, user-intuitive interface ...
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... Others offer time slicing in which each task runs for a given period of time and then must switch tasks, regardless of conditions. Still others claim to be fully preemptive, yet they do not allow any interrupt to cause a preemption. All of these models will fail at one point or another. © 2005 Microchip Technology Inc. offer only ...
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... Nested interrupts • All functions contained in a library • Interrupt-callable functions • Scalability • Free source code provided • Integrated with CMX-MicroNet™ for optional networking connectivity © 2005 Microchip Technology Inc. dsPIC30F FIGURE 12-4: CMX-TINY+ CONFIGURATION MANAGER 12.6.2 CMX-TINY+™ ...
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... Can serve up Java applets • No proprietary protocols • Runs stand-alone or with any RTOS • Economical one-time fee • Full source code provided is • No royalties on shipped products • Excellent documentation and support FIGURE 12-5: CMX-MICRONET USER INTERFACE © 2005 Microchip Technology Inc. ...
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... RAM (not including buffer sizes) UDP/SLIP 56 bytes TCP/HTTP/PPP 304 bytes Ethernet 38 bytes © 2005 Microchip Technology Inc. dsPIC30F 12.8 Soft Modem Application Library Microchip offers V.22/V.22bis (1200/2400 bps) and V.32/V.32bis (9600/14400 bps) ITU-T specifications to support a range of “connected” applications. Applications that will benefit from these modem specifications include: • ...
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... The physical layer is integrated into the communication controller’s hardware and is not covered by the OSEK specifications. Vector Informatik GmbH has created a dsPIC30F architecture version of their osCAN interfaces for along with various support utilities. software and ® operating system, © 2005 Microchip Technology Inc. ...
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... MCU sample. Easy to plug in and remove from development board. * Prices are subject to change without notice. © 2005 Microchip Technology Inc. dsP IC 30F peripherals and supports M icrochip’ In-C ircuit D ebugger ( tool for cost effective debugging and program m ing of the dsP IC 30F device ...
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... LED connected to pin RD0 for status indicator • All device I/O pins are brought out to a header for test point and prototyping access • Prototype area for user hardware FIGURE 13-2: dsPICDEM 28-PIN STARTER DEMO BOARD © 2005 Microchip Technology Inc. tool for the Digital Signal comprise ...
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... FIGURE 13-3: dsPICDEM 1.1 DEVELOPMENT BOARD © 2005 Microchip Technology Inc. 13.4 Motor Control Development Board The dsPIC30F Motor Control Development Board provides three main components for quick prototyping and validation of BLDC, PMAC and ACIM applications: • ...
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... There are presently two different plug-in sample types that support the 80-pin TQFP package types, for general purpose (dsPIC30F6014A) and dsPIC30F6010A samples. The use of plug-in samples is considered interim development board mechanization. © 2005 Microchip Technology Inc. motor control ...
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... Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power © 2005 Microchip Technology Inc. Table A-1 provides a brief description of device I/O pinouts and functions that can be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’ ...
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... UART1 Alternate Transmit. ST UART2 Receive. — UART2 Transmit. — Positive supply for logic and I/O pins. — Ground reference for logic and I/O pins. Analog Analog Voltage Reference (High) input. Analog Analog Voltage Reference (Low) input. Description © 2005 Microchip Technology Inc. ...
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... Pin Diagrams 18-Pin PDIP and SOIC AN0/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin SDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 © 2005 Microchip Technology Inc. MCLR +/CN2/RB0 REF SS AN1/V -/CN3/RB1 16 AN6/SCK1/INT0/OCFA/RB6 REF 3 15 ...
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... INT0/RA11 17 24 IC2/INT2/RD9 18 23 OC4/RD3 AN9/RB9 AN10/RB10 AN11/RB11 AN12/RB12 EMUC2/OC1/RD0 EMUD2/OC2/RD1 RF0 RF1 U2RX/RF4 U2TX/RF5 U1RX/SDI1/SDA/RF2 EMUD3/U1TX/SDO1/SCL/RF3 EMUC3/SCK1/RF6 IC1/INT1/RD8 RD2 AN9/CSCK/RB9 AN10/CSDI/RB10 AN11/CSDO/RB11 AN12/COFS/RB12 EMUC2/OC1/RD0 EMUD2/OC2/RD1 C1RX/RF0 C1TX/RF1 U2RX/RF4 U2TX/RF5 U1RX/SDI1/SDA/RF2 EMUD3/U1TX/SDO1/SCL/RF3 EMUC3/SCK1/RF6 IC1/INT1/RD8 OC3/RD2 V DD © 2005 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 44-Pin TQFP AN4/CN6/RB4 AN5/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 AN8/RB8 OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 © 2005 Microchip Technology Inc dsPIC30F3014 dsPIC30F AN12/RB12 EMUC2/OC1/RD0 EMUD2/OC2/RD1 RF0 RF1 U2RX/RF4 U2TX/RF5 U1RX/SDI1/SDA/RF2 DS70043F-page 67 ...
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... Pin Diagrams (Continued) 44-Pin TQFP AN4/IC7/CN6/RB4 AN5/IC8/CN7/RB5 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 AN8/RB8 OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 DS70043F-page dsPIC30F4013 AN12/COFS/RB12 EMUC2/OC1/RD0 EMUD2/OC2/RD1 C1RX/RF0 C1TX/RF1 U2RX/RF4 U2TX/RF5 U1RX/SDI1/SDA/RF2 © 2005 Microchip Technology Inc. ...
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... TQFP COFS/RG15 1 T2CK/RC1 2 T3CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF © 2005 Microchip Technology Inc. 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F5011 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 dsPIC30F DS70043F-page 69 ...
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... T5CK/RC4 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 DS70043F-page dsPIC30F5013 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2005 Microchip Technology Inc. ...
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... TQFP RG15 1 T2CK/RC1 2 T3CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF © 2005 Microchip Technology Inc. 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F6011A 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 dsPIC30F DS70043F-page 71 ...
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... TQFP COFS/RG15 1 T2CK/RC1 2 T3CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF DS70043F-page 72 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F6012A 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 © 2005 Microchip Technology Inc. ...
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... T2CK/RC1 2 3 T3CK/RC2 4 T4CK/RC3 T5CK/RC4 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 © 2005 Microchip Technology Inc dsPIC30F6013A dsPIC30F EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 ...
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... T5CK/RC4 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 DS70043F-page dsPIC30F6014A EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2005 Microchip Technology Inc. ...
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... SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC/EMUC/AN1/V -/CN3/RB1 15 REF PGD/EMUD/AN0/V +/CN2/RB0 16 REF * This device is not recommened for new designs. See dsPIC30F6011A. © 2005 Microchip Technology Inc. 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F6011* 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 ...
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... AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 PGC/EMUC/AN1/V -/CN3/RB1 15 REF PGD/EMUD/AN0/V +/CN2/RB0 16 REF * This device is not recommened for new designs. See dsPIC30F6012A. DS70043F-page 76 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F6012* 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 © 2005 Microchip Technology Inc. ...
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... T5CK/RC4 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 * This device is not recommened for new designs. See dsPIC30F6013A. © 2005 Microchip Technology Inc dsPIC30F6013 dsPIC30F EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 ...
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... AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 * This device is not recommened for new designs. See dsPIC30F6014A. DS70043F-page dsPIC30F6014 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2005 Microchip Technology Inc. ...
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... Legend: CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power © 2005 Microchip Technology Inc. Table B-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. ...
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... Synchronous serial data input/output for I 32 kHz low-power oscillator crystal input; CMOS otherwise. 32 kHz low-power oscillator crystal output. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input © 2005 Microchip Technology Inc. ...
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... EMUC3/AN1/V AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1//RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 © 2005 Microchip Technology Inc. Description UART1 Receive. UART1 Transmit. UART1 Alternate Receive. UART1 Alternate Transmit. UART2 Receive. UART2 Transmit. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. ...
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... REF 2 39 -/CN3/RB1 REF 3 38 PWM1L/RE0 4 37 PWM1H/RE1 AN3/INDX/CN5/RB3 PWM2L/RE2 5 36 PWM2H/RE3 6 35 PWM3L/RE4 7 34 AN6/OCFA/RB6 PWM3H/RE5 AN7/RB7 AN8/RB8 C1RX/RF0 C1TX/RF1 OSC1/CLKI 28 U2RX/RF4 13 U2TX/RF5 OSC2/CLKO/RC15 14 27 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 26 PGD/EMUD/U1TX/SDO1/SCK/RF3 16 25 SCK1/RF6 FLTA/INT0/RE8 EMUC2/OC1/IC1/INT1/RD0 OC4/RD3 19 22 OC3/RD2 © 2005 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 44-Pin TQFP AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 © 2005 Microchip Technology Inc dsPIC30F3011 dsPIC30F PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 RF0 RF1 U2RXRF4 U2TX/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 DS70043F-page 83 ...
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... Pin Diagrams (Continued) 44-Pin TQFP AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 OSC1/CLKI OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 DS70043F-page dsPIC30F4011 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 C1RX/RF0 C1TX/RF1 U2RXRF4 U2TX/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 © 2005 Microchip Technology Inc. ...
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... TQFP PWM3H/RE5 1 PWM4L/RE6 2 PWM4H/RE7 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF © 2005 Microchip Technology Inc. 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 INT4/RD11 44 INT3/RD10 43 IC2/FLTB/INT2/RD9 42 IC1/FLTA/INT1/RD8 dsPIC30F5015 OSC2/CLKO/RC15 39 OSC1/CLKIN SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 dsPIC30F DS70043F-page 85 ...
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... TQFP PWM3H/RE5 1 PWM4L/RE6 2 PWM4H/RE7 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/QEB/IC8/CN7/RB5 11 AN4/QEA/IC7/CN6/RB4 12 AN3/INDX/CN5/RB3 13 AN2/SS1/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF DS70043F-page 86 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/FLTB/INT2/RD9 42 IC1/FLTA/INT1/RD8 dsPIC30F6015 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 © 2005 Microchip Technology Inc. ...
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... PWM4H/RE7 4 T2CK/RC1 T4CK/RC3 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 FLTA/INT1/RE8 13 FLTB/INT2/RE9 14 AN5/QEB/CN7/RB5 15 AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 Note: Pinout subject to change. © 2005 Microchip Technology Inc dsPIC30F6010A dsPIC30F EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 ...
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... AN4/QEA/CN6/RB4 16 AN3/INDX/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 * This device is not recommened for new designs. See dsPIC30F6010A. DS70043F-page dsPIC30F6010 EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUD2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 SDA/RG3 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 U1RX/RF2 U1TX/RF3 © 2005 Microchip Technology Inc. ...
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... NOTES: © 2005 Microchip Technology Inc. dsPIC30F DS70043F-page 89 ...
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