M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 86

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 7.5 External Bus Operation with Software Wait State (2)
0
2
1
9
C
3 .
B
8 /
0
1
0
3
(1) Separate Bus with 3 Wait States
(2) Multiplexed Bus with 2 Wait States
(3) Multiplexed Bus with 3 Wait States
3
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G
4
a
NOTES:
0 -
n
o r
3 .
Write Signal
Read Signal
Data Bus
BCLK
Write Signal
Address Bus/Data Bus
Chip-Select Signal
BCLK
Write Signal
1. This example illustrates bus cycle length. Read cycle and write cycle may occur consecutively.
BCLK
Address Bus
Chip-Select
Signal
ALE
Address Bus
Read Signal
Address Bus
Address Bus/
Data Bus
ALE
Chip-Select
Signal
Read Signal
1
2. The address bus and chip-select signal may be extended depending on CPU state such as an
3. When the microcomputer continuously accesses the same external space (same CS area), the chip-
u
, 1
3
p
1
instruction queue buffer.
select signal may be output continuously.
2
(
0
M
(2, 3)
(2, 3)
0
3
6
(2)
2
C
(2)
8 /
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Address
M
(2, 3)
3
2
(2)
C
f o
8 /
4
8
3
Address
Bus cycle
Bus cycle
8
) T
Address
Address
Data output
Data output
(1)
Bus cycle
(1)
Address
Data output
(1)
Address
Address
Address
Bus cycle
Bus cycle
Address
Address
Bus cycle
(1)
(1)
Input
(1)
Input
Input
7. Bus