M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 156

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 13.4 Relocatable Vector and DMAC II Index
2
0
13.4.4 Chained Transfer
13.4.5 End-of-Transfer Interrupt
C
1
9
3 .
B
8 /
(1) Transfer, caused by a transfer request factor, occurs according to the content of the DMAC II index.
(2) When COUNT reaches "0", the contents of CADR1 to CADR0 are written to the vector of the request
(3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the
The CHAIN bit in MOD selects the chained transfer.
The following process initiates the chained transfer.
Figure 13.4 shows the relocatable vector and DMACII index of when the chained transfer is in progress.
For the chained transfer, the relocatable vector table must be located in the RAM.
The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer
interrupt service routine in the IADR1 to IADR0 bits. The end-of-transfer interrupt is generated when
COUNT reaches "0."
0
1
3
0
The vectors of the request factor indicates the address where the DMAC II index is allocated. For each
request, the BRST bit in MOD selects either single or burst transfer.
factor. When the INTE bit in the MOD is set to "1," the end-of-transfer interrupt is generated simulta-
neously.
DMAC II index indicated by the vector rewritten in (2).
3
J
G
4
a
o r
0 -
n
3 .
1
u
, 1
3
p
1
(
2
M
0
0
3
Relocatable vector
6
2
C
DMAC II
Index(2)
DMAC II
Index(1)
8 /
Page 131
, 3
M
3
2
C
f o
8 /
4
3
8
INTB
BASE(1)
(CADR1 to
BASE(2)
(CADR1 to
CADR0)
CADR0)
) T
8
BASE(2)
BASE(3)
RAM
Peripheral I/O interrupt vector causing DMAC II request
Default value of DMAC II is BASE(1).
The above vector is rewritten to BASE(2)
when a transfer is completed.
Starts at BASE(2) when next request conditions
are met.
Transferred according to the DMAC II Index.
The above vector is rewritten to BASE(3)
when a transfer is completed.
13. DMACII