M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 222

• Manufacturer Part Number: M30833FJGP#U3
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 87
• Interface Type: UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Table 16.13 Registers To Be Used and Settings (I
2
0
Register
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR
i=0 to 4
1
9
C
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
3 .
1
u
, 1
3
p
1
0 to 7
0 to 7
8
ABT
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1 to CLK0
CRS
TXEPT
CRD, NCH
CKPOL
UFORM
TE
TI
RE
RI
UiRRM, UiLCH,
UiERE
IICM
ABC
BBS
3 to 7
IICM2
CSC
SWC
ALS
STC
SWC2
SDHI
SU1HIM
SSE
CKPH
DINC, NODC, ERR Set to "0"
DL2 to DL0
STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
IFSR6, IFSR7
2
(
M
0
0
3
6
2
C
Bit
Page 197
8 /
, 3
M
3
2
C
f o
8 /
Set transmit data
Received data can be read
ACK or NACK bit can be read
Arbitration lost detect flag
Overrun error flag
Set bit rate
Set to "010
Set to "0"
Set to "0"
Select count source of the UiBRG register
Disabled because CRD = 1
Transfer register empty flag
Set to "1"
Set to "0"
Set to "1"
Set to "1" to enable data transmission
Transfer buffer empty flag
Set to "1" to enable data reception
Reception complete flag
Set to "0"
Set to "1"
Select an arbitration lost detect timing
Bus busy flag
Set to "00000
See Table 16.14
Set to "1" to enable clock synchronization
Set to "1" to output fixed "L" from the SDAi on the falling edge of the ninth bit of
the transfer clock
Set to "1" to terminate SDA output when
detecting the arbitration lost
Not used. Set to "0"
Set to "1" to forcibly output an "L" signal from SCL
Set to "1" to disable SDA output
Set to "0"
Set to "0"
See Table 16.14.
Set digital delay value
Set to "1" when generating start condition
Set to "1" when generating restart condition
Set to "1" when generating stop condition
Set to "1" when using a condition generating function
Select ACK or NACK
Set to "1" to output ACK data
Set to "1" to enable SCL output stop when
detecting stop condition
Not used. Set to "0"
Set to "1"
4
3
8
) T
8
2
"
2
"
Master
2
C Mode)
Function
16. Serial I/O (Special Function)
Disabled
Disabled
Set to "1"
Disabled
Disabled
Set to "0"
Not used. Set to "0"
Set to "1" to reset UARTi
by detecting a start condition
Not used. Set to "0"
Not used. Set to "0"
Set to "1" to output fixed "L" from SCLi
on the falling edge of the ninth bit of
the transfer clock
Slave