HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 77

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.2.14 BLD
Notes
For the @aa:8 access range, refer to the relevant microcontroller hardware manual.
BLD (Bit LoaD)
Operation
(<Bit No.> of <EAd>)
Assembly-Language Format
BLD #xx:3, <EAd>
Operand Size
Byte
Description
This instruction loads a specified bit from the destination operand into the carry bit. The bit
number is specified by 3-bit immediate data. The destination operand contents remain unchanged.
Available Registers
Rd:
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Note: * The addressing mode is the addressing mode of the destination operand <EAd>.
Register direct
Register indirect
Absolute address
Addressing
Mode *
R0L to R7L, R0H to R7H
Mnemonic
BLD
BLD
BLD
<EAd>
C
Bit No.
#xx:3,Rd
#xx:3,@ERd
#xx:3,@aa:8
Operands
7
Specified by #xx:3
1st byte
7
7
7
C
E
7
Condition Code
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Loaded from the specified bit.
0 IMM
0 erd
2nd byte
— —
I
Instruction Format
Rev. 3.00 Dec 13, 2004 page 61 of 258
abs
UI
rd
0
C
Section 2 Instruction Descriptions
— —
H
3rd byte
7
7
0
U
7
7
—
N
0 IMM
0 IMM
REJ09B0213-0300
—
4th byte
Z
—
V
0
0
Bit Load
C
States
No. of
2
6
6