HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 117

IC H8 MCU FLASH 56K 64LQFP

HD64F3687GFPV

Manufacturer Part Number
HD64F3687GFPV
Description
IC H8 MCU FLASH 56K 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheets

Specifications of HD64F3687GFPV

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
56KB (56K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
Package
64LQFP
Family Name
H8
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
45
Interface Type
I2C/SCI
On-chip Adc
8-chx10-bit
Number Of Timers
3
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3687GFPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3687GFPV
Manufacturer:
RENESAS
Quantity:
1 000
2.2.29 (2) EXTS (L)
Notes
EXTS (EXTend as Signed)
Operation
(<Bit 15> of ERd)
ERd>)
Assembly-Language Format
EXTS.L ERd
Operand Size
Longword
Description
This instruction copies the sign of the lower 16 bits (general register Rd) in a 32-bit register ERd
in the upward direction (copies ERd bit 15 to bits 31 to 16) to extend the data to signed longword
data.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Register direct
Addressing
Mode
Don’t care
Mnemonic
EXTS.L
16 bits
(<bits 31 to 16> of
ERd
Sign bit
Operands
ERd
16 bits
1st byte
1
7
Condition Code
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Previous value remains unchanged.
Sign extension
2nd byte
F
cleared to 0.
cleared to 0.
Instruction Format
— —
Rev. 3.00 Dec 13, 2004 page 101 of 258
I
0 erd
16 bits
UI
Section 2 Instruction Descriptions
H
ERd
3rd byte
U
16 bits
N
4th byte
REJ09B0213-0300
Z
Sign Extension
V
0
States
No. of
C
2

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