HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 36

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 CPU
Type
Arithmetic
operations
Rev. 3.00 Dec 13, 2004 page 20 of 258
REJ09B0213-0300
Instruction
ADDS
SUBS
DAA
DAS
MULXS
MULXU
DIVXS
DIVXU
CMP
NEG
Size *
L
B
B/W
B/W
B/W
B/W
B/W/L
B/W/L
Function
Rd ± 1
Adds or subtracts the value 1, 2, or 4 to or from data in
a 32-bit register.
Rd decimal adjust
Decimal-adjusts an addition or subtraction result in a
general register by referring to the CCR to produce 4-
bit BCD data.
Rd
Performs signed multiplication on data in two general
registers: either 8 bits
bits
Rd
Performs unsigned multiplication on data in two general
registers: either 8 bits
bits
Rd ÷ Rs
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits
bit remainder or 32 bits ÷ 16 bits
16-bit remainder.
Rd ÷ Rs
Performs unsigned division on data in two general
registers: either 16 bits ÷ 8 bits
bit remainder or 32 bits ÷ 16 bits
16-bit remainder.
Rd – Rs, Rd – #IMM
Compares data in a general register with data in
another general register or with immediate data, and
sets the CCR according to the result.
0 – Rd
Takes the two’s complement (arithmetic complement)
of data in a general register.
Rs
Rs
32 bits.
32 bits.
Rd, Rd ± 2
Rd
Rd
Rd
Rd
Rd
Rd
8 bits
8 bits
Rd, Rd ± 4
16 bits or 16 bits
16 bits or 16 bits
8-bit quotient and 8-
8-bit quotient and 8-
16-bit quotient and
16-bit quotient and
Rd
16
16