HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 37

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Type
Arithmetic
operations
Logic operations AND
Shift operations
Instruction
EXTS
EXTU
OR
XOR
NOT
SHAL
SHAR
SHLL
SHLR
ROTL
ROTR
ROTXL
ROTXR
Size *
W/L
W/L
B/W/L
B/W/L
B/W/L
B/W/L
B/W/L
B/W/L
B/W/L
B/W/L
Function
Rd (sign extension)
Extends byte data in the lower 8 bits of a 16-bit register
to word data, or extends word data in the lower 16 bits
of a 32-bit register to longword data, by extending the
sign bit.
Rd (zero extension)
Extends byte data in the lower 8 bits of a 16-bit register
to word data, or extends word data in the lower 16 bits
of a 32-bit register to longword data, by padding with
zeros.
Rd
Performs a logical AND operation on a general register
and another general register or immediate data.
Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate
data.
¬ (Rd)
Takes the one’s complement of general register
contents.
Rd (shift)
Performs an arithmetic shift on general register
contents.
Rd (shift)
Performs a logical shift on general register contents.
Rd (rotate)
Rotates general register contents.
Rd (rotate)
Rotates general register contents through the carry bit.
Rs
Rs
Rs
(Rd)
Rd, Rd
Rd, Rd
Rd, Rd
Rd
Rd
Rd
Rd
Rev. 3.00 Dec 13, 2004 page 21 of 258
#IMM
#IMM
#IMM
Rd
Rd
Rd
Rd
Rd
REJ09B0213-0300
Section 1 CPU