EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 724
EP9307-CRZ
Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-CRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
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- Download datasheet (13Mb)
23
Respect to SCLKIN in Microwire Mode
23-12
Synchronous Serial Port
EP93xx User’s Guide
23.5.11.1 Setup and Hold Time Requirements on SFRMIN with
SSPRXD
SSPTXD
SFRM
SCLK
In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge
of SCLKIN after SFRMIN has gone LOW. Masters that drive a free-running SCLKIN must
ensure that the SFRMIN signal has sufficient setup and hold margins with respect to the
rising edge of SCLKIN.
Figure 23-11
rising edge on which the first bit of receive data is to be sampled by the SSP slave, SFRMIN
must have a setup of at least two times the period of SCLKIN on which the SSP operates.
With respect to the SCLKIN rising edge previous to this edge, SFRMIN must have a hold of
at least one SCLKIN period.
S S P R X D
Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements
S F R M IN
S C L K IN
LSB
illustrates these setup and hold time requirements. With respect to the SCLKIN
0
Figure 23-10. Microwire Frame Format (Continuous Transfers)
MSB
4 to 16 bits output data
t
clkm ax
Copyright 2007 Cirrus Logic
t
h o ld
= t
0
S S P C L K IN
LSB
MSB
sam p led b y S S P slave
F irst R X d ata b it to b e
M S B
8-bit control
t
setup
= (2t
S S P C L K IN
)
LSB
MSB
DS785UM1
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