EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 229

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

ScrnLines
LineLength
DS785UM1
31
15
31
15
Address: 0x8003_0030
Default: 0x0000_0000
Definition: Video Screen Lines Register
Bit Descriptions:
Address: 0x8003_0034
Default: 0x0000_0000
Definition: Video Line Length Register
Bit Descriptions:
30
14
30
14
RSVD
RSVD
29
13
29
13
28
12
28
12
PAGE:
NA:
RSVD:
LINES:
RSVD:
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Video Screen Half-page Starting SDRAM Address -
Read/Write
If DSCAN = ‘1’ in the
Half-page Starting SDRAM Address value written to this
field corresponds to the upper left corner of the bottom half
of the video screen.
Not Assigned. Will return written value during a read.
Reserved - Unknown during read
Lines - Read/Write
The Lines value written to this field specifies the number of
lines to be scanned to the display during normal and half-
page mode operation.
Reserved. Unknown during read.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
24
8
8
RSVD
RSVD
23
23
7
7
22
22
6
6
PixelMode
LINES
LEN
21
21
5
5
20
20
4
4
register, the Video Screen
19
19
3
3
EP93xx User’s Guide
18
18
2
2
17
17
1
1
16
16
7-47
0
0
7