EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 627

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

SIRTR0
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
DMAERR:
TXDMAE:
RXDMAE:
0x808B_0030 - Read/Write
0x0000_0000, except that bit 4 is unknown at reset
IrDA Slow InfraRed Test Register 0.
RSVD:
SIREN:
SIROUT:
TXD:
RXD:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the IrDA receive section. If “1”,
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include framing errors, receive
abort, and CRC mismatch.
TX DMA interface enable. Setting to “1” enables the
private DMA interface to the transmit FIFO.
RX DMA interface enable. Setting to “1” enables the
private DMA interface to the receive FIFO.
Reserved. Unknown During Read.
The state of the SIREN after synchronization. Read only.
The state of SIROUT output from the InfraRed block. Read
only.
The state of the TXD input to the InfraRed block from
UART2. Read only.
The state of the RXD output from the InfraRed block to
UART2. Read only.
24
8
RSVD
SIREN
23
7
SIROUT
22
6
TXD
21
5
RXD
20
4
SIRT
19
3
EP93xx User’s Guide
SIRIN
18
2
S16CLK
17
1
TSIRC
17-31
IrDA
16
0
17