EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 795
EP9307-CRZ
Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-CRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
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- Download datasheet (13Mb)
DS785UM1
28.1.3 Reset
All GPIO registers are initialized on system reset. The data and data direction registers for all
ports (except as noted below) are cleared, configuring them as inputs. Port E[1:0] bits are
used for the LED outputs RDLED and GRLED respectively and are set to drive high. Port
G[3:2] bits are used for SLA[1:0] outputs and are set to drive low. Port G[1:0] bits are used
for EEDAT and EECLK respectively and are set up as inputs. All interrupt control and
debounce registers are cleared.
to PRDATA[7:0]
Figure 28-3. Signal Connections Within the Enhanced GPIO Port Control Logic
Enhanced GPIO Ports A, B, and F
DDR
DR
TISR
DB
INTEN
INTTYPE1
INTTYPE2
Register
Read
Select
DATA
EDGE
Copyright 2007 Cirrus Logic
ENA
POL
OE
OE
OE
(Ports A, B, F)
TESTRDSEL
1
0
INTERRUPT
CONTROL
LOGIC
TESTINPSEL
OE[7:0]
DATA[7:0]
0
1
CLK
IN
EP93xx User’s Guide
EP[7:0]
GPIO Interface
ICLK
28-5
28
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