EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 169

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

DS785UM1
CLK1HZ
V_SYNC
INT_VIDEO_FIFO Video FIFO Interrupt. See
INT_SSP1RX
INT_SSP1TX
TC3UI
INT_UART1
SSPINTR
INT_UART2
INT_UART3
USHINTR
INT_PME
Copyright 2007 Cirrus Logic
1 Hz clock interrupt. See
With Software
Vertical or Composite Sync/Frame Pulse Interrupt. See
Chapter
Timing and
Analog/LCD Integrated Timing and Interface"
SSP Receive Interrupt. See
Serial
SSP Transmit Interrupt. See
Serial
Timer Counter 3 Underflow Interrupt. This interrupt
becomes active on the next falling edge of the timer
counter 3 clock after the timer counter has under flowed
(reached zero). The interrupt is cleared by writing any
value to the
"Timers".
UART 1 General Interrupt. This interrupt is active if any
UART1 interrupt is active. Interrupt service routines will
need to read the relevant status bits within UART1 to
determine the source of the interrupt. All these sources
are individually maskable within UART1. See
“UART1”.
Synchronous Serial Port (SSP) Interrupt. See
"Synchronous Serial
UART 2 General Interrupt. This interrupt is active if any
UART2 interrupt is active. Interrupt service routines will
need to read the relevant status bits within UART2 to
determine the source of the interrupt. All these sources
are individually maskable within UART2. See
"UART2".
UART 3 General Interrupt. This interrupt is active if any
UART3 interrupt is active. Interrupt service routines will
need to read the relevant status bits within UART3 to
determine the source of the interrupt. All these sources
are individually maskable within UART3. See
"UART3 With HDLC
USB Host Interrupt. See
Controller”.
PME interrupt. See
Port".
Port".
Port".
7,
Interface".
"Raster Engine With Analog/LCD Integrated
“Timer3Clear”
Trim".
Chapter 23 "Synchronous Serial
Encoder".
Port".
Chapter
Chapter
Chapter
register. See
Chapter 23 "Synchronous
Chapter 23 "Synchronous
Vectored Interrupt Controller
11, “USB Host
20,
7,
"Raster Engine With
"Real Time Clock
EP93xx User’s Guide
Chapter
Chapter
Chapter
Chapter
Chapter 23
18,
15,
16,
15,
6-7
6