EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 589

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

UART3HDLCCtrl
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
RSVD
FLAG
29
13
28
12
0:
0x808E_020C - Read/Write
0x0000_0000
HDLC Control Register
RSVD:
CMAS:
TXCM:
RXCM:
TXENC:
CMAS
CRCN
27
11
CRCApd
TXCM
26
10
Copyright 2007 Cirrus Logic
RXCM
IDLE
25
9
Must be written as “0”.
Reserved. Unknown During Read.
Clock Master:
1 - Transmitter and/or receiver use 1x clock generated by
the internal transmitter.
0 - Transmitter and/or receiver use 1x clock generated
externally.
Transmit Clock Mode.
1 - Generate 1x clock when in synchronous HDLC mode
using NRZ encoding.
0 - Do not generate clock.
This bit has no effect unless TXENC is clear and
synchronous HDLC is enabled.
Receive Clock Mode.
1 - Use external 1x clock when in synchronous HDLC
mode using NRZ encoding.
0 - Do not use external clock.
This bit has no effect unless RXENC is clear and
synchronous HDLC is enabled.
Transmit Encoding method.
1 - Use Manchester bit encoding.
0 - Use NRZ bit encoding.
This bit has no effect unless synchronous HDLC is
enabled
TXENC
24
8
AME
RXENC
23
7
SYNC
22
6
RSVD
TFCEN
21
5
TABEN
RXE
20
4
UART3 With HDLC Encoder
RFCEN
TXE
19
3
EP93xx User’s Guide
RILEN
TUS
18
2
RFLEN
CRCE
17
1
RTOEN
16-13
CRCS
16
0
16