EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 348
EP9307-CRZ
Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-CRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
- Current page: 348 of 824
- Download datasheet (13Mb)
9
SelfCtl
9-46
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
RSVD
31
15
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
Note: Clause 22.2.2.1 in the IEEE-802-3 specification states that the maximum MDC clock rate
Note: The user must check the datasheet of the PHY being used in the design. If the PHY needs
30
14
is 2.5 MHz. Most PHYs support clock rates faster than 2.5 MHz. So, modify the MDCDIV
value according to the PHYs specification.
a preamble for reading/writing to/from PHY registers, the PSPRS must be cleared (set to
0).
29
13
28
12
PB:
STxON:
0x8001_0020 - Read/Write
0x0000_0F10
0x0000_0000
Self Control Register
RSVD:
MDCDIV:
PSPRS:
MDCDIV
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Pause Busy: This bit remains set as long as a pause
frame is being transmitted. Only one pause frame may be
sent at any time, therefore the Send Pause and Pause
Busy bits should be zero before a new pause frame is
defined.
Serial Transmit ON. The transmitter is enabled when set.
When clear, no transmissions are allowed. When a frame
is being transmitted, and STxON is cleared, then that
transmit frame is completed. No subsequent frames are
transmitted until STxON is set again.
Reserved. Unknown During Read.
MDC Clock Divisor. HCLK is divided by MDCDIV + 1 to
create the MDC clock frequency. Default value is 0x07,
which is divide by 8.
Preamble Suppress. Default is 1.
1 = The first MDC qualifies an SFD on MDIO.
0 = Get 32 ones before SFD.
PSPRS
24
8
RSVD
RWP
23
7
RSVD
22
6
GPO0
21
5
PUWE
20
4
PDWE
19
3
MIIL
18
2
RSVD
17
1
DS785UM1
RESET
16
0
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