EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 241

• Manufacturer Part Number: EP9307-CRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1138

DS785UM1
S:
P:
M3
S2
P2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
Table 7-14. Blink Mode Definition Table (Continued)
M2
S1
1
1
1
1
1
1
1
P1
0
0
1
1
0
0
1
1
0
0
1
1
Table 7-16. Bits per Pixel Scanned Out
Table 7-15. Output Shift Mode Table
M1
0
1
1
0
0
1
1
Copyright 2007 Cirrus Logic
S0
P0
0
1
0
1
0
1
0
1
0
1
0
1
Shift - Read/Write
The Shift Mode is specified by selecting a value from
Table 7-15
Pixel - Read/Write
The number of bits per pixel that are output on the P[x]
pins is specified by selecting a value from
writing it to this field.
The Graphics Engine has a separate setting for this value,
which may or may not be the same.
M0
Raster Engine With Analog/LCD Integrated Timing and Interface
1
0
1
0
1
0
1
Dual Scan 2 2/3 3-bit pixels per clock over 8-bit bus
2 - pixels per shift clock (up to 9 bits wide each)
4 - pixels per shift clock (up to 4 bits wide each)
8 - pixels per shift clock (up to 2 bits wide each)
Undefined - Defaults to 1 - pixel per pixel clock
1 - pixel mapped to 18 bits each pixel clock
1 - pixel per pixel clock (up to 24 bits wide)
2 2/3 3-bit pixels per clock over 8 bit bus
Blink to offset color 888 mode (555,565)
Blink to offset color single value mode
and writing it to this field.
pixel multiplexer disabled
Blink brighter 888 mode (555,565)
Blink dimmer 888 mode (555,565)
Blink dimmer single value mode
Blink brighter single value mode
4 bits per pixel
8 bits per pixel
Pixel Mode
Shift Mode
do not use
Blink Mode
Undefined
EP93xx User’s Guide
Table 7-16
and
7-59
7