LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 6

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
1.5 Block diagram
UM10375
User manual
Fig 1.
DTR, DSR
DCD
(1) LPC1342/43 only.
(2) LQFP48 package only.
CT32B0_MAT[3:0]
CT32B1_MAT[3:0]
CT16B0_MAT[2:0]
CT16B1_MAT[1:0]
GPIO ports
PIO0/1/2/3
CT32B0_CAP0
CT32B1_CAP0
CT16B0_CAP0
CT16B1_CAP0
(2)
LPC13xx block diagram
, RI
(2)
(2)
, CTS,
, RTS
RXD
TXD
HIGH-SPEED
GPIO
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
I-code
bus
CORTEX-M3
TEST/DEBUG
INTERFACE
UART
SWD
ARM
D-code
bus
All information provided in this document is subject to legal disclaimers.
slave
system
bus
AHB-LITE BUS
Rev. 2 — 7 July 2010
CONTROLLER
BRIDGE
AHB TO
USB DEVICE
USB PHY
APB
USB pins
slave
slave
(1)
(1)
LPC1311/13/42/43
Chapter 1: LPC13xx Introductory information
SYSTEM CONTROL
WDO
POR
IRC
10-bit ADC
IOCONFIG
8/16/32 kB
I
2
FLASH
C-BUS
WDT
SSP
slave
XTALOUT
POWER CONTROL,
slave
slave
GENERATION,
FUNCTIONS
clocks and
SYSTEM
XTALIN
CLOCK
controls
SRAM
4/8 kB
ROM
RESET
002aae722
UM10375
© NXP B.V. 2010. All rights reserved.
AD[7:0]
SCL
SDA
CLKOUT
SCK
SSEL
MISO
MOSI
7 of 333