LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 48

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
UM10375
User manual
3.10.4.1 Normal mode
3.10.4 Frequency selection
spikes or drops in the frequency of the output clock. The recommended way of changing
between divider settings is to power down the PLL, adjust the divider settings and then let
the PLL start up again.
The PLL frequency equations use the following parameters (also see
Table 54.
In this mode the post divider is enabled, giving a 50% duty cycle clock with the following
frequency relations:
To select the appropriate values for M and P, it is recommended to follow these steps:
Table 55
SYSPLLCTRL or USBPLLCTRL registers
equivalent to the system clock if the system clock divider SYSAHBCLKDIV is set to one
(see
Parameter
FCLKIN
FCCO
FCLKOUT
P
M
1. Specify the input clock frequency Fclkin.
2. Calculate M to obtain the desired output frequency Fclkout with M = F
3. Find a value so that FCCO = 2 × P × F
4. Verify that all frequencies and divider values conform to the limits specified in
and
Table
Table
shows how to configure the PLL for a 12 MHz crystal oscillator using the
PLL frequency parameters
22).
10.
All information provided in this document is subject to legal disclaimers.
System PLL
Frequency of sys_pllclkin (input clock
to the system PLL) from the
SYSPLLCLKSEL multiplexer (see
Section
Frequency of the Current Controlled
Oscillator (CCO); 156 to 320 MHz.
Frequency of sys_pllclkout
System PLL post divider ratio; PSEL
bits in SYSPLLCTRL (see
Section
System PLL feedback divider register;
MSEL bits in SYSPLLCTRL (see
Section
Rev. 2 — 7 July 2010
Fclkout
3.5.11).
3.5.3).
3.5.3).
=
M
×
Fclkin
(Table 8
clkout
Chapter 3: LPC13xx System configuration
.
=
(
or
FCCO
Table
USB PLL
Frequency of usb_pllclkin (input clock
to the USB PLL) from the
USBPLLCLKSEL multiplexer (see
Section
Frequency of the Current Controlled
Oscillator (CCO); 156 to 320 MHz.
Frequency of usb_pllclkout
USB PLL post divider ratio; PSEL bits
in USBPLLCTRL (see
USB PLL feedback divider register;
MSEL bits in USBPLLCTRL (see
Section
)
⁄
9). The main clock is
(
3.5.23).
3.5.5).
2
×
P
)
Figure
UM10375
© NXP B.V. 2010. All rights reserved.
clkout
Section
3):
/ F
clkin
Table 8
49 of 333
3.5.5).
.
(1)