LPC1342FHN33,551 NXP Semiconductors, LPC1342FHN33,551 Datasheet - Page 167

• Manufacturer Part Number: LPC1342FHN33,551
• Description: IC MCU 32BIT 16KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1342FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4946; 935289656551

NXP Semiconductors
Table 186. Register overview: UART (base address: 0x4000 8000)
[1]
UM10375
User manual
Name
U0RBR
U0THR
U0DLL
U0DLM
U0IER
U0IIR
U0FCR
U0LCR
U0MCR
U0LSR
U0MSR
U0SCR
U0ACR
-
U0FDR
-
U0TER
-
U0RS485CTRL R/W
U0ADRMATCH R/W
U0RS485DLY
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Access Address
RO
WO
R/W
R/W
R/W
RO
WO
R/W
R/W
RO
RO
R/W
R/W
-
R/W
-
R/W
-
R/W
offset
0x000
0x000
0x000
0x004
0x004
0x008
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034 -
0x048
0x04C
0x050
0x054
Description
Receiver Buffer Register. Contains the next received character
to be read.
Transmit Holding Register. The next character to be transmitted
is written here.
Divisor Latch LSB. Least significant byte of the baud rate
divisor value. The full divisor is used to generate a baud rate
from the fractional rate divider.
Divisor Latch MSB. Most significant byte of the baud rate
divisor value. The full divisor is used to generate a baud rate
from the fractional rate divider.
Interrupt Enable Register. Contains individual interrupt enable
bits for the 7 potential UART interrupts.
Interrupt ID Register. Identifies which interrupt(s) are pending.
FIFO Control Register. Controls UART FIFO usage and modes. 0x00
Line Control Register. Contains controls for frame formatting
and break generation.
Modem control register
Line Status Register. Contains flags for transmit and receive
status, including line errors.
Modem status register
Scratch Pad Register. Eight-bit temporary storage for software. 0x00
Auto-baud Control Register. Contains controls for the
auto-baud feature.
Reserved
Fractional Divider Register. Generates a clock input for the
baud rate divider.
Reserved
Transmit Enable Register. Turns off UART transmitter for use
with software flow control.
Reserved
RS-485/EIA-485 Control. Contains controls to configure various
aspects of RS-485/EIA-485 modes.
RS-485/EIA-485 address match. Contains the address match
value for RS-485/EIA-485 mode.
RS-485/EIA-485 direction control delay.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 11: LPC13xx UART
UM10375
Reset
Value
NA
NA
0x01
0x00
0x00
0x01
0x00
0x00
0x60
0x00
0x00
-
0x10
-
0x80
-
0x00
0x00
0x00
© NXP B.V. 2010. All rights reserved.
[1]
-
-
Notes
when
DLAB=0
when
DLAB=0
when
DLAB=1
when
DLAB=1
when
DLAB=0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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